Altera Cyclone V - ECRC Forwarding; Clock Signals; Reset Signals

5–14 Chapter 5: IP Core Interfaces
ECRC Forwarding
Cyclone V Hard IP for PCI Express November 2011 Altera Corporation
ECRC Forwarding
On the Avalon-ST interface, the ECRC field follows the same alignment rules as
payload data. For packets with payload, the ECRC is appended to the data as an extra
dword of payload. For packets without payload, the ECRC field follows the address
alignment as if it were a one dword payload. Depending on the address alignment,
Figure 5–5 on page 5–6 through Figure 5–8 on page 5–8 illustrate the position of the
ECRC data for RX data. Figure 5–9 on page 5–11 through illustrate the position of
ECRC data for TX data. For packets with no payload data, the ECRC corresponds to
the position of Data0 in these figures.
Clock Signals
Table 5–5 describes the clock signals that comprise the clock interface.
Refer to Chapter 7, Reset and Clocks for more information about the clock interface.
Reset Signals
Table 5–6 describes the reset signals.
Table 5–5. Clock Signals Hard IP Implementation
(1)
Signal I/O Description
refclk I
Reference clock for the Cyclone V Hard IP for PCI Express. It must have the frequency
specified under the System Settings heading in the parameter editor.
pld_clk I Clocks the Application Layer. You must drive this clock with coreclkout .
coreclkout O
This is a fixed frequency clock used by the Data Link and Transaction Layers. To meet PCI
Express link bandwidth constraints, this clock has minimum frequency requirements as listed
in Table 7–1 on page 7–3.
Note to Table 5–5:
(1) Figure 7–2 on page 7–2 illustrates these clock signals.
Table 5–6. Reset and Link Training Signals (Part 1 of 3)
Signal I/O Description
npor I
Active high reset signal.
npor is an input to the embedded reset controller in Cyclone V
devices. You can control this reset input with software.
reset_status O
Reset Status signal. When asserted, this signal indicates that the Hard IP clock is in reset.
The
reset_status signal is synchronous to the pld_clk clock and is deasserted only
when the
pld_clk clock is stable. You should use reset_status to drive the reset of your
application.