Altera Cyclone V - Physical Layer Interface Signals; Transceiver Reconfiguration; Serial Interface Signals

5–32 Chapter 5: IP Core Interfaces
Physical Layer Interface Signals
Cyclone V Hard IP for PCI Express November 2011 Altera Corporation
Physical Layer Interface Signals
This section describes the global PHY support signals for the internal PHY. The
MegaWizard Plug-In Manager generates a SERDES variation file,
<variation>_serdes.<v or vhd >, in addition of the Hard IP variation file,
<variation>.<v or vhd>. For Cyclone V GX devices the SERDES entity is included in
the library files for PCI Express.
Transceiver Reconfiguration
Table 5–20 describes the transceiver support signals. In Table 5–20, <n> is the number
of lanes.
f For more information about the refer to the “Transceiver Reconfiguration Controller”
chapter in the Altera Transceiver PHY IP Core User Guide.
The following sections describe signals for the serial or parallel PIPE interfaces. The
PIPE interface is only available for simulation.
Serial Interface Signals
Table 5–21 describes the serial interface signals.
f Refer to Pin-out Files for Altera Devices for pin-out tables for all Altera devices in
.pdf, .txt, and .xls formats.
Table 5–20. Transceiver Control Signals
Signal Name I/O Description
reconfig_fromxcvr[(<n>70)-1:0]
reconfig_toxcvr[(<n>46)-1:0]
O
These are the parallel transceiver dynamic reconfiguration buses.
Dynamic reconfiguration is required to compensate for variations due to
process, voltage and temperature (PVT). Among the analog settings that
you can reconfigure are: V
OD
, pre-emphasis, and equalization.
You can use the Altera Transceiver Reconfiguration Controller to
dynamically reconfigure analog settings in Cyclone V devices. For more
information about instantiating the Altera Transceiver Reconfiguration
Controller IP core refer to Chapter 13, Reconfiguration and Offset
Cancellation.
busy_xcvr_reconfig O
When asserted, indicates that the a reconfiguration operation is in
progress.
Table 5–21. 1-Bit Interface Signals
Signal I/O Description
tx_out [<n-1>:0]
(1)
O Transmit input. These signals are the serial outputs.
rx_in [<n-1>:0]
(1)
I Receive input. These signals are the serial inputs.
Note to Table 5–21:
(1) <n> = 1 for the ×1 IP core. <n> = 4 for the ×4 IP core.