Altera Cyclone V - Configuration Space Register Access Timing

Chapter 5: IP Core Interfaces 5–23
Transaction Layer Configuration Space Signals
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Configuration Space Register Access Timing
Figure 5–15 shows typical traffic on the
tl_cfg_ctl bus. The tl_cfg_add index
increments on the rising edge of
coreclkout , specifying which Configuration Space
register information is being driven onto
tl_cfg_ctl .
[29:25] cfg_prmcsr_func0[31:27]
Records the following 5 primary command status errors:
■ Detected parity error
■ Received system error
■ Received master abort
■ Received target abort
■ Signalled target abort.
[24]
cfg_prmcsr_func0[24] Primary command status error bit, data parity reported.
[23:6]
cfg_rootcsr[25:8]
Records the following PME status information:
■ PME pending
■ PME status
■ PME request ID[15:0]
[5:1]
cfg_seccsr[31:27]
Records the following 5 secondary command status errors:
■ Detected parity error
■ Received system error
■ Received master abort
■ Received target abort
■ Signalled target abort
[0]
cfg_seccsr[24] 6th primary command status error bit.
Table 5–12. Mapping Between tl_cfg_sts and Configuration Space Registers (Part 2 of 2)
tl_cfg_sts[122:0] Correspondence Description
Figure 5–15. tl_cfg_ctl Timing
coreclkout
tl_cfg_add[3:0]
tl_cfg_ctl[31:0]
2 3 4 5 6 7 8 9 A B 8 9 A B C D E
..
00... 00... 00... 7F...
00000000 00000000
00... 00...