Chapter 13: Debugging 13–3
Hardware Bring-Up Issues
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Use Third-Party PCIe Analyzer
A third-party logic analyzer for PCI Express records the traffic on the physical link
and decodes traffic, saving you the trouble of translating the symbols yourself. A
third-party s logic analyzer can show the two-way traffic at different levels for
different requirements. For high-level diagnostics, the analyzer shows the LTSSM
flows for devices on both side of the link side-by-side. This display can help you see
the link training handshake behavior and identify where the traffic gets stuck. A
traffic analyzer can display the contents of packets so that you can verify the contents.
For complete details, refer to the third-party documentation.
BIOS Enumeration Issues
Both FPGA programming (configuration) and the initialization of a PCIe link require
time. There is some possibility that Altera FPGA including a Hard IP block for PCI
Express may not be ready when the OS/BIOS begins enumeration of the device tree.
If the FPGA is not fully programmed when the OS/BIOS begins its enumeration, the
OS does not include the Hard IP for PCI Express in its device map. To eliminate this
issue, you can do a soft reset of the system to retain the FPGA programming while
forcing the OS/BIOS to repeat its enumeration.
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