Altera Cyclone V - P_Clk; Coreclkout; Pld_Clk

Chapter 7: Reset and Clocks 7–3
Clocks
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
As Figure 7–2 indicates, there are three clock domains:
■ p_clk
■ coreclkout
■ pld_clk
p_clk
The transceiver derives p_clk from the 100 MHz refclk signal that you must provide
to the device. The PCI Express Base Specification 2.1 requires that the
refclk signal
frequency be 100 MHz
±300 PPM; however, as a convenience, you can also use a
reference clock that is 125 MHz
±300 PPM.
The CDC module implements the asynchronous clock domain crossing between the
PHY/MAC
p_clk domain and the Data Link Layer coreclk domain.
coreclkout
The coreclkout signal is derived from p_clk . Table 7–1 lists frequencies for
coreclkout which are a function of the link width, data rate, and the width of the
Avalon-ST bus.
The frequencies and widths specified in Table 7–1 are maintained throughout
operation. If the link downtrains to a lesser link width or changes to a different
maximum link rate, it maintains the frequencies it was originally configured for as
specified in Table 7–1. (The Hard IP throttles the interface to achieve a lower
throughput.)
pld_clk
This clock drives the Transaction Layer, Data Link Layer, part of the PHY/MAC
Layer, and the Application Layer. Ideally, the
pld_clk drives all user logic in the
Application Layer, including other instances of the Cyclone V Hard IP for PCI Express
and memory interfaces. The
pld_clk input clock pin is typically generated from the
coreclkout_hip output clock pin.
Table 7–1. coreclkout Values for All Parameterizations
Link Width Max Link Rate Avalon Interface Width coreclkout_hip
×1 Gen1 64 125 MHz
×1 Gen1 64 62.5 MHz
(1)
×4 Gen1 64 125 MHz
Note to Table 7–1:
(1) This mode saves power.