Chapter 4: IP Core Architecture 4–7
Protocol Layers
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
The DLL has the following sub-blocks:
■ Data Link Control and Management State Machine—This state machine is
synchronized with the Physical Layer’s LTSSM state machine and also connects to
the Configuration Space Registers. It initializes the link and flow control credits
and reports status to the Configuration Space.
■ Data Link Layer Packet Generator and Checker—This block is associated with the
DLLP’s 16-bit CRC and maintains the integrity of transmitted packets.
■ Transaction Layer Packet Generator—This block generates transmit packets,
generating a sequence number and a 32-bit CRC (LCRC). The packets are also sent
to the retry buffer for internal storage. In retry mode, the TLP generator receives
the packets from the retry buffer and generates the CRC for the transmit packet.
■ Retry Buffer—The retry buffer stores TLPs and retransmits all unacknowledged
packets in the case of NAK DLLP reception. For ACK DLLP reception, the retry
buffer discards all acknowledged packets.
■ ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and
generates the sequence number of transmitted packets.
■ Transaction Layer Packet Checker—This block checks the integrity of the received
TLP and generates a request for transmission of an ACK/NAK DLLP.
■ TX Arbitration—This block arbitrates transactions, prioritizing in the following
order:
a. Initialize FC Data Link Layer packet
b. ACK/NAK DLLP (high priority)
c. Update FC DLLP (high priority)
d. PM DLLP
e. Retry buffer TLP
f. TLP
g. Update FC DLLP (low priority)
h. ACK/NAK FC DLLP (low priority)
Physical Layer
The Physical Layer is the lowest level of the Cyclone V Hard IP for PCI Express. It is
the layer closest to the link. It encodes and transmits packets across a link and accepts
and decodes received packets. The Physical Layer connects to the link through a
high-speed SERDES interface running at 2.5 Gbps for Gen1 implementations .
The Physical Layer is responsible for the following actions:
■ Initializing the link
■ Scrambling/descrambling and 8B/10B encoding/decoding of 2.5 Gbps (Gen1) per
lane 8B/10B
■ Serializing and deserializing data
■ Operating the PIPE 2.0 Interface
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