Chapter 10: Interrupts 10–3
Interrupts for Endpoints
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Figure 10–4 illustrates the interactions among MSI interrupt signals for the Root Port
in Figure 10–3. The minimum latency possible between
app_msi_req
and
app_msi_ack
is one clock cycle.
MSI-X
You can enable MSI-X interrupts by turning on Implement MSI-X on the MSI-X tab
under the PCI Express/PCI Capabilities heading using the parameter editor. If you
turn on the Implement MSI-X option, you should implement the MSI-X table
structures at the memory space pointed to by the BARs as part of your Application
Layer.
MSI-X TLPs are generated by the Application Layer and sent through the TX
interface. They are single dword memory writes so that
Last DW Byte Enable
in the
TLP header must be set to 4b’0000. MSI-X TLPs should be sent only when enabled by
the MSI-X enable and the function mask bits in the message control for MSI-X
Configuration register. These bits are available on the
tl_cfg_ctl
output bus.
f For more information about implementing the MSI-X capability structure, refer
Section 6.8.2. of the PCI Local Bus Specification, Revision 3.0.
Legacy Interrupts
Legacy interrupts are signaled on the PCI Express link using message TLPs that are
generated internally by the Cyclone V Hard IP for PCI Express IP core. The
app_int_sts
input port controls interrupt generation. When the input port asserts
app_int_sts
, it causes an
Assert_INTA
message TLP to be generated and sent
upstream. Deassertion of the
app_int_sts
input port causes a
Deassert_INTA
message
TLP to be generated and sent upstream. To use legacy interrupts, you must clear the
Interrupt Disable
bit, which is bit 10 of the
Command
register (Table 6–2 on page 6–2).
Then, turn off the
MSI Enable
bit (Table 5–15 on page 5–27.)
Figure 10–4. MSI Interrupt Signals Waveform
(1)
Note to Figure 10–4:
(1)
app_msi_req
can extend beyond
app_msi_ack
before deasserting. F
coreclkout
app_msi_req
app_msi_tc[2:0]
app_msi_num[4:0]
app_msi_ack
123 56
4
valid
valid
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