Chapter 5: IP Core Interfaces 5–17
ECC Error Signals
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Figure 5–14 illustrates the timing relationship between
npor
and the LTSSM L0s state.
ECC Error Signals
Table 5–7 describes the ECC error signals. Refer to Chapter 11, Interrupts for detailed
information about all interrupt mechanisms.
Interrupts for Endpoints
Table 5–8 describes the IP core’s interrupt signals for Endpoints. These signals are
level sensitive. Refer to Chapter 10, Interrupts for descriptions of all interrupt
mechanisms.
Figure 5–14. 100 ms Requirement
npor
IO_POF_Load
PCIe_LinkTraining_Enumeration
dl_ltssm[4:0]
detect.
quiet
detect.active
polling.active
L0
100 ms (maximum)
Table 5–7. ECC Error Signals for Hard IP Implementation
(1)
Signal I/O Description
derr_cor_ext_rcv0
O
Indicates a corrected error in the RX buffer. This signal is for debug only. It
is not valid until the RX buffer is filled with data.
derr_cor_ext_rcv1
O This signal is not used and can be tied to ground.
derr_rpl
O
Indicates an uncorrectable error in the retry buffer. This signal is for debug
only.
derr_cor_ext_rpl
O
Indicates a corrected ECC error in the retry buffer. This signal is for debug
only.
Note to Table 5–7:
(1) The Avalon-ST
rx_st_err
described in Table 5–2 on page 5–3 indicates an uncorrectable error in the RX buffer.
Table 5–8. Interrupt Signals for Endpoints (Part 1 of 2)
Signal I/O Description
tl_app_msi_req
I
Application Layer MSI request. Assertion causes an MSI posted write TLP to be generated
based on the MSI configuration register values and the tl_
app_msi_tc
and
app_msi_num
input ports.
tl_app_msi_ack
O
Application Layer MSI acknowledge. This signal acknowledges the Application Layer's
request for an MSI interrupt.
tl_app_msi_tc[2:0]
I
Application Layer MSI traffic class. This signal indicates the traffic class used to send the
MSI (unlike INTX interrupts, any traffic class can be used to send MSIs).
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