Altera Cyclone V - Page 68

5–16 Chapter 5: IP Core Interfaces
Reset Signals
Cyclone V Hard IP for PCI Express November 2011 Altera Corporation
currentspeed[1:0] O
Indicates the current speed of the PCIe link. The following encodings are defined:
■ 2b’00: Reserved
■ 2b’01: Gen1
■ 2b’10: Gen2
■ 2b’11: Gen3
dl_ltssm[4:0] O
LTSSM state: The LTSSM state machine encoding defines the following states:
■ 00000: detect.quiet
■ 00001: detect.active
■ 00010: polling.active
■ 00011: polling.compliance
■ 00100: polling.configuration
■ 00101: polling.speed
■ 00110: config.linkwidthstart
■ 00111: config.linkaccept
■ 01000: config.lanenumaccept
■ 01001: config.lanenumwait
■ 01010: config.complete
■ 01011: config.idle
■ 01100: recovery.rcvlock
■ 01101: recovery.rcvconfig
■ 01110: recovery.idle
■ 01111: L0
■ 10000: disable
■ 10001: loopback.entry
■ 10010: loopback.active
■ 10011: loopback.exit
■ 10100: hot.reset
■ 10101: L0s
■ 10110: L1.entry
■ 10111: L1.idle
■ 11000: L2.idle
■ 11001: L2.transmit.wake
■ 11010: recovery.speed
Table 5–6. Reset and Link Training Signals (Part 3 of 3)
Signal I/O Description