Altera Cyclone V - Modifying the Example Design

Chapter 2: Getting Started 2–19
Modifying the Example Design
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Modifying the Example Design
To use this example design as the basis of your own design, replace the Chaining
DMA Example shown in Figure 2–7 with your own Application Layer design. Then,
create a Root Port BFM driver to generate the transactions needed to test your
Application Layer.
.
Figure 2–7. Testbench for PCI Express
PCB
Hard IP for PCI Express
Altera FPGA
PCB
Transaction Layer
Data Link Layer
PHY MAC Layer
x4 PCIe Link
(Physical Layer)
PHY IP Core for PCI Express
Lane 2
Lane 3
Lane 4
Lane 1
Lane 0
TX PLL
Transceiver Bank
S
Reconfig
to and from
Transceiver
to and from
Embedded
Controller
(Avalon-MM
slave interface)
Transceiver
Reconfiguration
Controller
Root
Port
BFM
Reset
APPS DUT
Chaining DMA
(User Application)
npor