Altera Cyclone V - Specifying the Parameters for the Cyclone V Hard IP for PCI Express

2–10 Chapter 2: Getting Started
Qsys Design Flow
Cyclone V Hard IP for PCI Express November 2011 Altera Corporation
The following sections provide step-by-step instructions to create the example design
in Qsys. If you prefer, you can copy the completed system from the Quartus II
software installation, and then go to “Generating the Simulation Model Using Qsys”
on page 2–16. The completed Qsys systems are located in the following directory:
<install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/example_design/cv.
Specifying the Parameters for the Cyclone V Hard IP for PCI Express
This section guides you through the process of specifying parameters for the Cyclone
V Hard IP for PCI Express to create a Gen1 ×4 Endpoint.
1. Specify the System Settings parameters listed in Table 2–9.
1 Each function shares the parameter settings on the Device, Error Reporting, Link,
Slot, and Power Management tabs. Each function has separate parameter settings for
the Base Address Registers, Base and Limit Registers for Root Ports, Device
Identification Registers, and the PCI Express/PCI Capabilites parameters. When
you click on a Func<n> tab under the Port Functions heading, the tabs automatically
reflect the Func<n> tab selected.
2. Specify the Device parameters listed in Table 2–10.
3. On the Error Reporting tab, leave all options off.
Table 2–9. System Settings Parameters
Parameter Value
Number of Lanes ×4
Lane Rate Gen 1 (2.5 Gbps)
Port type Native endpoint
Application interface Avalon-ST 64-bit
RX buffer credit allocation - performance for
received requests
Low
Reference clock frequency 100 MHz
Use 62.5 MHz Application Layer clock for ×1 Leave this option Off
Use deprecated RX Avalon-ST data byte enable
port (rx_st_be)
Leave this option On.
Number of functions 1
Table 2–10. Device
Parameter Value
Maximum payload size 256 bytes
Number of tags supported 32
Completion timeout range ABCD
Implement completion timeout disable On