Altera Cyclone V - Error Reporting

Chapter 3: Parameter Settings 3–5
Port Functions
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Error Reporting
Table 3–3 describes the Advanced Error Reporting (AER) and ECRC parameters.
Completion
timeout range
(continued)
The following encodings are used to specify the range:
■ 0001 Range A
■ 0010 Range B
■ 0011 Ranges A and B
■ 0110 Ranges B and C
■ 0111 Ranges A, B, and C
■ 1110 Ranges B, C and D
■ 1111 Ranges A, B, C, and D
All other values are reserved. Altera recommends that the
completion timeout mechanism expire in no less than 10 ms.
Implement
completion
timeout disable
0x0A8
On/Off On
For PCI Express version 2.0 and higher Endpoints, this option
must be On. The timeout range is selectable. When On, the
core supports the completion timeout disable mechanism via
the PCI Express
Device Control Register 2 . The
Application Layer logic must implement the actual completion
timeout mechanism for the required ranges.
Table 3–2. Capabilities Registers for Function <n> (Part 2 of 2)
Parameter
Possibl
e
Values
Default
Value
Description
Table 3–3. Error Reporting 0x800–0x834
Parameter Value
Default
Value
Description
Advanced error
reporting (AER)
On/Off Off When On, enables the AER capability.
ECRC checking On/Off Off
When On, enables ECRC checking. Sets the read-only value of the
ECRC check capable bit in the
Advanced Error Capabilities
and Control Register
. This parameter requires you to enable the
AER capability.
ECRC generation On/Off Off
When On, enables ECRC generation capability. Sets the read-only
value of the ECRC generation capable bit in the
Advanced Error
Capabilities and Control Register
. This parameter requires
you to enable the AER capability.
ECRC forwarding On/Off Off
When On, enables ECRC forwarding to the Application Layer. On the
Avalon-ST RX path, the incoming TLP contains the ECRC dword
(1)
and the
TD bit is set if an ECRC exists. On the transmit the TLP from
the Application Layer must contain the ECRC dword and have the
TD
bit set.
Note to Table 3–3:
(1) Throughout The Cyclone V Hard IP for PCI Express User Guide, the terms word, dword and qword have the same meaning that they have in the
PCI Express Base Specification Revision 2.1 or 3.0. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.