Altera Cyclone V - ECRC on the TX Path; Lane Initialization and Reversal

9–2 Chapter 9: Optional Features
Lane Initialization and Reversal
Cyclone V Hard IP for PCI Express November 2011 Altera Corporation
ECRC on the TX Path
When the ECRC generation option is on, the TX path generates ECRC. If you turn on
ECRC forwarding, the ECRC value is forwarded with the TLP. Table 9–2 summarizes
the TX ECRC generation and forwarding. In this table, if
TD is 1, the TLP includes an
ECRC.
TD is the TL digest bit of the TL packet described in Appendix A, Transaction
Layer Packet (TLP) Header Formats.
Lane Initialization and Reversal
Connected components that include IP blocks for PCI Express need not support the
same number of lanes. The ×4 variations support initialization and operation with
components that have 1, 2, or 4 lanes.
Yes
No
none No Forwarded
good No Forwarded with its ECRC
bad No Forwarded with its ECRC
Yes
none No Forwarded
good No Forwarded with its ECRC
bad Yes Not forwarded
Note to Table 9–1:
(1) The ECRC Check Enable is in the Configuration Space Advanced Error Capabilities and Control
Register.
Table 9–1. ECRC Operation on RX Path (Part 2 of 2)
ECRC
Forwarding
ECRC
Check
Enable
(1)
ECRC
Status
Error TLP Forward to Application Layer
Table 9–2. ECRC Generation and Forwarding on TX Path
(1)
ECRC
Forwarding
ECRC
Generation
Enable
(2)
TLP on Application
Layer
TLP on Link Comments
No
No
TD =0, without ECRC TD =0, without ECRC
TD =1, without ECRC TD =0, without ECRC
Yes
TD =0, without ECRC TD =1, with ECRC
ECRC is generated
TD =1, without ECRC TD =1, with ECRC
Yes
No
TD =0, without ECRC TD =0, without ECRC
Core forwards the
ECRC
TD =1, with ECRC TD =1, with ECRC
Yes
TD =0, without ECRC TD =0, without ECRC
TD =1, with ECRC TD =1, with ECRC
Notes to Table 9–2:
(1) All unspecified cases are unsupported and the behavior of the Hard IP is unknown.
(2) The
ECRC Generation Enable is in the Configuration Space Advanced Error Capabilities and
Control
Register.