Chapter 4: IP Core Architecture 4–5
Protocol Layers
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
3. TLPs are stored in a specific part of the RX buffer depending on the type of
transaction (posted, non-posted, and completion).
4. The TLP FIFO block stores the address of the buffered TLP.
5. The receive reordering block reorders the queue of TLPs as needed, fetches the
address of the highest priority TLP from the TLP FIFO block, and initiates the
transfer of the TLP to the Application Layer.
6. When ECRC generation and forwarding are enabled, the Transaction Layer
forwards the ECRC dword to the Application Layer.
Tracing a transaction through the TX datapath involves the following steps:
1. The Transaction Layer informs the Application Layer that sufficient flow control
credits exist for a particular type of transaction using the TX credit signals. The
Application Layer may choose to ignore this information.
2. The Application Layer requests permission to transmit a TLP. The Application
Layer must provide the transaction and must be prepared to provide the entire
data payload in consecutive cycles.
3. The Transaction Layer verifies that sufficient flow control credits exist and
acknowledges or postpones the request.
4. The Transaction Layer forwards the TLP to the Data Link Layer.
Configuration Space
The Configuration Space implements the following Configuration Space Registers
and associated functions:
■ Header Type 0 Configuration Space for Endpoints
■ Header Type 1 Configuration Space for Root Ports
■ PCI Power Management Capability Structure
■ Message Signaled Interrupt (MSI) Capability Structure
■ Message Signaled Interrupt–X (MSI–X) Capability Structure
■ PCI Express Capability Structure
■ Advanced Error Reporting (AER) Capability Structure
The Configuration Space also generates all messages (PME#, INT, Error, Slot Power
Limit), MSI requests, and completion packets from configuration requests that flow in
the direction of the root complex, except Slot Power Limit messages, which are
generated by a downstream port. All such transactions are dependent upon the
content of the PCI Express Configuration Space as described in the PCI Express Base
Specification Revision 2.1.
Refer To “Configuration Space Register Content” on page 6–1 or Chapter 7 in the PCI
Express Base Specification 2.1 for the complete content of these registers.
To Next Page
Loading...
