Altera Cyclone V - Reset and Clocks; Reset

November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
7. Reset and Clocks
This chapter covers the functional aspects of the reset and clock circuitry for the
Cyclone V Hard IP for PCI Express. It includes the following sections:
■ Reset
■ Clocks
For descriptions of the available reset and clock signals refer to the following sections:
“Reset Signals” on page 5–14, and “Clock Signals” on page 5–14.
Reset
The Cyclone V Hard IP for PCI Express IP core includes an embedded reset controller
to handle the initial reset of the PMA, PCS, and Hard IP for PCI Express IP core. The
pin_perst signal which is driven from one of the two designated nPERST pins of the
device initiates reset. Figure 7–1 provides a high-level view of the reset hardware.
As Figure 7–1 indicates, the reset controller receives information about the current
LTSSM state from the Hard IP and drives global and specialized resets to the Hard IP.
After reset is complete, all port registers and state machines are set to their
initialization values with the exception of sticky registers as defined Sections 7.4 and
7.6 of the PCI Express Base Specification. The reset outputs of the reset controller affect
varying amounts of the state of the Hard IP block as follows:
Figure 7–1. Reset Controller for Cyclone V Devices
<variant>.v or .vhd
Transceiver Reset
State Machine
Configuration Space
Sticky Registers
Datapath State Machines of
MegaCore Function
Configuration Space
Non-Sticky Registers
crst
srst
pin_perst
frefclk
(derived from
refclk )
rst
Reset
Controller
Transceiver
Reconfiguration
Controller
npor npor
l2_exit
hotrst_exit
dlup_exit
dlup
ltssmstate[4:0]
serdes_pll_locked
pld_clk_inuse
pld_core_ready
fixedclk_locked
busy_xcvr_reconfig
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