Chapter 9: Optional Features 9–3
Lane Initialization and Reversal
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
The Cyclone V Hard IP for PCI Express supports lane reversal, which permits the
logical reversal of lane numbers for the ×1, ×2, and ×4. Lane reversal allows more
flexibility in board layout, reducing the number of signals that must cross over each
other when routing the PCB.
Table 9–3 summarizes the lane assignments for normal configuration.
Table 9–4 summarizes the lane assignments with lane reversal.
Figure 9–1 illustrates a PCI Express card with ×4 IP Root Port and a ×4 Endpoint on
the top side of the PCB. Connecting the lanes without lane reversal creates routing
problems. Using lane reversal, solves the problem.
Table 9–3. Lane Assignments without Lane Reversal
Lane Number 3 2 1 0
×4 IP core 3 2 1 0
×1 IP core — — — 0
Table 9–4. Lane Assignments with Lane Reversal
Core Config 4 1
Slot Size 8 4 2 18421
Lane
assignments
7:0,6:1,5:2,4:3 3:0,2:1,1:2,0:3 3:0,2:1 3:0 7:0 3:0 1:0 0:0
Figure 9–1. Using Lane Reversal to Solve PCB Routing Problems
0
1
2
3
Root Port
3
2
1
0
Endpoint
0
1
2
3
Root Port
0
1
2
3
Endpoint
No Lane Reversal
Results in PCB Routing Challenge
With Lane Reversal
Signals Route Easily
lane
reversal
no lane
reversal
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