Altera Cyclone V - Page 128

13–2 Chapter 13: Debugging
Hardware Bring-Up Issues
Cyclone V Hard IP for PCI Express November 2011 Altera Corporation
Check Link Training and Status State Machine (ltssmstate[4:0])
The
ltssmstate[4:0] bus encodes the status of LTSSM. The LTSSM state machine
reflects the Physical Layer’s progress through the link training process. For a
complete description of the states these signals encode, refer to “Reset and Link
Training Signals” on page 5–14. When link training completes successfully and the
link is up, the LTSSM should remain stable in the L0 state.
When link issues occur, you can monitor
ltssmstate[4:0] to determine whether link
training fails before reaching the L0 state or the link was initially established (L0), but
then lost due to an additional link training issue. If you have link training issues, you
can check the actual link status in hardware using the SignalTap II logic analyzer. The
LTSSM encodings indicate the LTSSM state of the Physical Layer as it proceeds
through the link training process.
f For more information about link training, refer to the “Link Training and Status State
Machine (LTSSM) Descriptions” section of PCI Express Base Specification 2.0.
f For more information about SignalTap, refer to the Design Debugging Using the
SignalTap II Embedded Logic Analyzer chapter in volume 3 of the Quartus II Handbook.
Check PIPE Interface
Because the LTSSM signals reflect the behavior of one side of the PCI Express link,
you may find it difficult to determine the root cause of the link issue solely by
monitoring these signals. Monitoring the PIPE interface signals in addition to the
ltssmstate bus provides greater visibility.
The PIPE interface is specified by Intel. This interface defines the MAC/PCS
functional partitioning and defines the interface signals for these two sublayers. Using
the SignalTap logic analyzer to monitor the PIPE interface signals provides more
information about the devices that form the link.
During link training and initialization, different pre-defined Physical Layer Packets
(PLPs), known as ordered sets are exchanged between the two devices on all lanes. All
of these ordered sets have special symbols (K codes) that carry important information
to allow two connected devices to exchange capabilities, such as link width, link data
rate, lane reversal, lane-to-lane de-skew, and so on. You can track the ordered sets in
the link initialization and training on both sides of the link to help you diagnose link
issues. You can use SignalTap logic analyzer to determine the behavior. The following
signals are some of the most important for diagnosing bring-up issues:
■ txdata< n> [15:0] / txdatak< n> [1:0] —These signals show the data and control
being transmitted from the Cyclone V Hard IP for PCI Express to the other device.
■ rxdata< n> [15:0] / rxdatak< n> [1:0] —These signals show the data and control
received by Hard P block from the other device.
■ phystatus< n>—This signal communicates completion of several PHY requests.
■ rxstatus< n> [2:0] —This signal encodes receive status and error codes for the
receive data stream and receiver detection.
You can monitor the PIPE signals through the
test_out bus.
f The PHY Interface for PCI Express Architecture specification is available on the Intel
website (www.intel.com).