Altera Cyclone V - Page 74

5–22 Chapter 5: IP Core Interfaces
Transaction Layer Configuration Space Signals
Cyclone V Hard IP for PCI Express November 2011 Altera Corporation
Table 5–12 describes the bits of the tl_cfg_sts bus for all eight functions and the
correspondence between the
tl_cfg_sts bus and the cfg_devcsr_func<n>
cfg_prmcsr_func<n>
registers. Refer to Table 5–13 on page 5–24 for the layout of the
configuration control and status information.
Table 5–12. Mapping Between tl_cfg_sts and Configuration Space Registers (Part 1 of 2)
tl_cfg_sts[122:0] Correspondence Description
func1[62:59]
func2[72:69]
func3[82:79]
func4[92:89]
func5[102:99]
func6[112:109]
func7[122:119]
cfg_devcsr_func<n>[19:16]
Records the following errors:
■ Unsupported request
■ Fatal error
■ Non-fatal error
■ Correctable error
func1[58:54]
func2[68:64]
func3[78:74]
func4[88:84]
func5[98:94]
func6[108:104]
func7[118:114]
cfg_prmcsr_func<n>[31:27]
Link status bits as follows:
■ Link autonomous bandwidth status
■ Link bandwidth management status
■ Data Link Layer link active
■ Slot clock configuration
func1[53]
func2[63]
func3[73]
func4[83]
func5[93]
func6[103]
func7[113]
cfg_prmcsr_func<n>[24] 6th primary command status error bit. Master data parity error.
[52:49]
cfg_devcsr_func0[19:16]
Records the following errors:
■ Unsupported request
■ Fatal error
■ Non-fatal error
■ Correctable error
[48]
cfg_slotcsr[24] Data Link Layer state changed.
[47]
cfg_slotcsr[20]
Command completed. (The hot plug controller completed a
command.)
[46:31]
cfg_linkcsr_func0[31:16]
Records the following link status information:
■ Link autonomous bandwidth status
■ Link bandwidth management status
■ Data Link Layer link active
■ Slot clock configuration
■ Link Training
■ Undefined
■ Negotiated Link Width (6 bits)
■ Link Speed (4 bits)
[30]
cfg_link2csr_func0[16] Records the current de-emphasis level.