Altera Cyclone V - Page 73

Chapter 5: IP Core Interfaces 5–21
Transaction Layer Configuration Space Signals
November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
tl_cfg_sts 123 0
Configuration status bits. This information updates every
pld_clk cycle. Bits[52:0]
record status information for function0. Bits[62:53] record information for function1.
Bits[72:63] record information for function 2, and so on. Refer to Table 5–12 for a
detailed description of the status bits.
tl_cfg_sts_wr 10
Write signal. This signal toggles when
tl_cfg_sts has been updated (every 8
core_clk cycles). The toggle marks the edge where tl_cfg_sts data changes. You
can use this edge as a reference to determine when the data is safe to sample.
hpg_ctrler
5I
The
hpg_ctrler signals are only available in Root Port mode and when the Slot
Capability register is enabled. Refer to the Use Slot register parameter in Table 3–5 on
page 3–6. For Endpoint variations the
hpg_ctrler input should be hardwired to 0s.
The bits have the following meanings:
[0] I
Attention button pressed. This signal should be asserted when the attention button is
pressed. If no attention button exists for the slot, this bit should be hardwired to 0, and
the
Attention Button Present bit (bit[0]) in the Slot Capability registerparameter
should be set to 0.
[1] I
Presence detect. This signal should be asserted when a presence detect circuit detects
a presence change in the slot.
[2] I
Manually-operated retention latch (MRL) sensor changed. This signal should be
asserted when an MRL sensor indicates that the MRL is Open. If an MRL Sensor does
not exist for the slot, this bit should be hardwired to 0, and the
MRL Sensor Present
bit (bit[2]) in the Slot Capability register parameter should be set to 0.
[3] I
Power fault detected. This signal should be asserted when the power controller detects
a power fault for this slot. If this slot has no power controller, this bit should be
hardwired to 0, and the
Power Controller Present bit (bit[1]) in the Slot Capability
register parameter should be set to 0.
[4] I
Power controller status. This signal is used to set the command completed bit of the
Slot Status register. Power controller status is equal to the power controller control
signal. If this slot has no power controller, this bit should be hardwired to 0 and the
Power Controller Present bit (bit[1]) in the Slot Capability register should be
disabled.
Table 5–11. Configuration Space Signals (Hard IP Implementation) (Part 2 of 2)
Signal Width Dir Description