November 2011 Altera Corporation Cyclone V Hard IP for PCI Express
5. IP Core Interfaces
This chapter describes the signals that are part of the Cyclone V Hard IP for PCI
Express IP core. Figure 5–1 on page 5–2 illustrates the top-level signals IP core.
Because the Cyclone V Hard IP for PCI Express offers exactly the same feature set in
the MegaWizard Plug-In Manager and Qsys design flows, your decision about which
design flow to use depends on whether you want to integrate the Cyclone V Hard IP
for PCI Express using RTL instantiation or Qsys. The Qsys system integration tool
automatically generates the interconnect logic between the IP components in your
system, saving time and effort. Refer to “MegaWizard Plug-In Manager Design Flow”
on page 2–3 and “Qsys Design Flow” on page 2–9 for a description of the steps
involved in the two design flows.
Table 5–1 lists each interface and provides a link to the subsequent sections that
describe each signal. The signals are described in the order in which they are shown in
Figure 5–1.
Table 5–1. Signal Groups in the Cyclone V Hard IP for PCI Express
Signal Group Description
Logical
Avalon-ST RX “Avalon-ST RX Interface” on page 5–3
Avalon-ST TX “Avalon-ST TX Interface” on page 5–8
Clock “Clock Signals” on page 5–14
Reset and link training “Reset Signals” on page 5–14
ECC error “ECC Error Signals” on page 5–17
Interrupt “Interrupts for Endpoints” on page 5–17
Interrupt and global error “Interrupts for Root Ports” on page 5–18
Configuration space “Transaction Layer Configuration Space Signals” on page 5–20
LMI “LMI Signals” on page 5–27
Completion “Completion Side Band Signals” on page 5–19
Power management “Power Management Signals” on page 5–30
Physical
Transceiver control “Transceiver Reconfiguration” on page 5–32
Serial “Serial Interface Signals” on page 5–32
PIPE
(1)
“PIPE Interface Signals” on page 5–33
Test
Test “Test Signals” on page 5–36
Note to Table 5–1:
(1) Provided for simulation only
November 2011
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