Altera MAX 10 - Page 3

Guideline: Output Clocks...............................................................................................................3-3
Guideline: PLL Cascading...............................................................................................................3-3
Guideline: Clock Switchover..........................................................................................................3-4
Guideline: .mif Streaming in PLL Reconfiguration.....................................................................3-5
Guideline: scandone Signal for PLL Reconfiguration.................................................................3-5
MAX 10 Clocking and PLL Implementation Guides......................................... 4-1
ALTCLKCTRL IP Core...............................................................................................................................4-1
IP Catalog and Parameter Editor...................................................................................................4-1
Specifying IP Core Parameters and Options................................................................................4-2
Files Generated for Altera IP Cores (Legacy Parameter Editor)...............................................4-4
ALTPLL IP Core.......................................................................................................................................... 4-5
IP Catalog and Parameter Editor...................................................................................................4-6
Specifying IP Core Parameters and Options................................................................................4-7
Files Generated for Altera IP Cores (Legacy Parameter Editor).............................................4-17
ALTPLL_RECONFIG IP Core.................................................................................................................4-18
IP Catalog and Parameter Editor.................................................................................................4-18
Specifying IP Core Parameters and Options..............................................................................4-19
Files Generated for Altera IP Cores (Legacy Parameter Editor).............................................4-20
Obtaining the Resource Utilization Report................................................................................4-21
Internal Oscillator IP Core....................................................................................................................... 4-21
IP Catalog and Parameter Editor.................................................................................................4-22
Specifying IP Core Parameters and Options..............................................................................4-23
Files Generated for Altera IP Cores (Legacy Parameter Editor).............................................4-24
ALTCLKCTRL IP Core References.....................................................................5-1
ALTCLKCTRL Parameters.........................................................................................................................5-1
ALTCLKCTRL Ports and Signals..............................................................................................................5-2
ALTPLL IP Core References............................................................................... 6-1
ALTPLL Parameters.................................................................................................................................... 6-1
Operation Modes Parameter Settings........................................................................................... 6-1
PLL Control Signals Parameter Settings.......................................................................................6-2
Programmable Bandwidth Parameter Settings............................................................................6-2
Clock Switchover Parameter Settings........................................................................................... 6-3
PLL Dynamic Reconfiguration Parameter Settings.................................................................... 6-4
Dynamic Phase Configuration Parameter Settings.....................................................................6-4
Output Clocks Parameter Settings.................................................................................................6-5
ALTPLL Ports and Signals..........................................................................................................................6-6
ALTPLL_RECONFIG IP Core References......................................................... 7-1
ALTPLL_RECONFIG Parameters............................................................................................................ 7-1
ALTPLL_RECONFIG Ports and Signals..................................................................................................7-2
ALTPLL_RECONFIG Counter Settings...................................................................................................7-7
TOC-3
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