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AMD XILINX VEK280 - Page 22

AMD XILINX VEK280
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3/20/24, 12:51 PM
Unofficial Document
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Boot Mode
Mode Pins [0:3]
2
Mode SW1 [1:4]
2
SD1 (SD 3.0) 0111 ON, OFF, OFF, OFF
1. Default switch setting.
2. Mode DIP SW1 poles [1:4] correspond to U1 XCVE2802 MODE[0:3].
3. Mode DIP SW1 individual switches ON=LOW (p/d to GND)=0, OFF=HIGH
(p/u to VCCO)=1.
JTAG
The AMD Vivado™ , AMD SDK, or third-party tools can establish a JTAG connection
to the Versal device in the two ways described in this section.
FTDI FT4232 USB-to-JTAG/USB-UART device (U20) connected to USB 2.0 type-
C connector (J369), which requires:
Set boot mode SW1 for JTAG as indicated in the "Mode Switch SW1
Configuration Option Settings" table in Versal Device Configuration.
On the 3-pin JTAG MUX, enable header J37 to enable the JTAG MUX.
Move the 2-pin jumper to be installed on pins 2-3. See Default Jumper
and Switch Settings for defaults and Board Component Location for
location.
Set 2-pole DIP SW3[1:2] set to 10 (OFF, ON) for JTAG MUX channel 2
FT4232 U20 bridge.
Power-cycle the VEK280 evaluation board or press the power-on reset
(POR) pushbutton (SW2). SW2 is near the USB-C JTAG port J369 in the
figure in Board Component Location).

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