Versal Device (U1) BankPower Supply Rail Net NameVoltage Description
FMCP1_LA[19:33],
FMCP1_CLK1_M2C
XPIO Bank
707
VCC1V1_LP4 1.1V LPDDR4 TRIP3 CH1
XPIO Bank
708
VCC1V1_LP4 1.1V LPDDR4 TRIP3 CH0
XPIO Bank
400
VCCO_HDIO_3V3 3.3V
(default)
PL_GEM0 MDIO/MDC,
PMOD_IO[0:7], PL_GEM0_RX/TX
XPIO Bank
401
VCCO_HDIO_3V3 3.3V
(default)
PL_GEM1_MDIO/MDC,
PL_GEM[0:1]_RST, SFP_TX_FAULT,
SFP_RX_LOS, UART1_TXD/RXD,
SYSCTLR_UART0, PL_GEM1_RX/TX
PMC MIO
500
VCCO_MIO 1.8V SYSMON, USB ULPI 2.0 interface,
OSPI interface
PMC MIO
501
VCCO_MIO 1.8V SD bus power, PCIe controls,
I2C0/21, UART0, CAN0_nSTB,
System Controller I2C/[trigger OR
CANFD0_INH], SD card controls,
GEM reset
LPD MIO
502
VCCO_502 1.8V GEM interface/controls, power
enables, PCIe PERST, fan tach, fan
PWM
1. The VEK280 board is shipped with VADJ_FMC set to 1.5V. This value
cannot be changed. Care must be taken when using FMC accessories.
See LPD MIO[23]: VADJ_FMC Power Rail for more details.
LPDDR4 Component Memory
[Figure 1, callout 2, 3, 4]
The VEK280 XCVE2802 device PL DDR memory interface performance is
documented in the Versal Premium Series Data Sheet: DC and AC Switching
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