AMD XILINX VEK280 - Page 26

3/20/24, 12:51 PM
Unofficial Document
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
26/78
‼
✎
I/O Voltage Rails
The XCVE2802 device PL I/O bank voltages on the VEK280 board are listed in the
following table.
Important: See LPD MIO[23]: VADJ_FMC Power Rail for more details on the
VADJ_FMC power rail.
Note: See the Versal Premium Series Data Sheet: DC and AC Switching
Characteristics (DS959) for more information. See the Versal Adaptive SoC
Technical Reference Manual (AM011) for more information about Versal device
configuration options.
Table: I/O Voltage Rails
Versal Device (U1) BankPower Supply Rail Net NameVoltage Description
XPIO Bank
700
VCC1V1_LP4 1.1V LPDDR4 TRIP1 CH0
XPIO Bank
701
VCC1V1_LP4 1.1V LPDDR4 TRIP1 CH1
XPIO Bank
702
VCC1V5_LP4 1.5V LPDDR4 TRIP1 CH0/1 reset, HDMI
control signals, GPIO LEDs
XPIO Bank
703
VCC1V1_LP4 1.1V LPDDR4 TRIP2 CH0
XPIO Bank
704
VCC1V1_LP4 1.1V LPDDR4 TRIP2 CH1
XPIO Bank
705
VADJ_FMC
1
1.5V LPDDR4 TRIP2 CH0/1 reset, HDMI
control signals, GPIO DIP,PB0/1,
SYSCTLR GPIO[0:7], SYS_CLK_1,
FMCP1_LA[00:01]_CC,
FMCP1_LA[02:16],FMCP_CLK0
XPIO Bank
706
VADJ_FMC
1
1.5V FMCP1_SYNC_M2C/C2M, LPDDR4
TRIP3 CH0/1 reset, SYS_CLK_2,
1588_GPIO[0:5],
FMCP1_REFCLK_C2M,
FMCP1_LA[17:18]_CC,