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AMD XILINX VEK280 - Page 31

AMD XILINX VEK280
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3/20/24, 12:51 PM
Unofficial Document
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
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The following table provides MIO peripheral mapping implemented on the VEK280
evaluation board. The Versal device bank 500, 501, and 502 mappings are listed in
the following table.
Table: MIO Peripheral Mapping
Bank MIO # Device Signal I/O Notes
500 0 OSPI PMC_MIO0_OSPI_CLK O
1 PMC_MIO1_OSPI_DQ0 I/O
2 PMC_MIO2_OSPI_DQ1 I/O
3 PMC_MIO3_OSPI_DQ2 I/O
4 PMC_MIO4_OSPI_DQ3 I/O
5 PMC_MIO5_OSPI_DQ4 I/O
6 PMC_MIO6_OSPI_DQS I/O
7 PMC_MIO7_OSPI_DQ5 I/O
8 PMC_MIO8_OSPI_DQ6 I/O
9 PMC_MIO9_OSPI_DQ7 I/O
10 PMC_MIO10_OSPI0_CS_BO
11 Regulator
Enable
GPIO
PMC_MIO11_VCC_AUX_1V2_ENO See Table 1
12 OSPI PMC_MIO12_OSPI_RST_BO
13 USB PMC_MIO13_USB_RST_B O
14 PMC_MIO14_USB_DAT0 I/O
15 PMC_MIO15_USB_DAT1 I/O
16 PMC_MIO16_USB_DAT2 I/O
17 PMC_MIO17_USB_DAT3 I/O

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