Bank MIO # Device Signal I/O Notes
See CAN
Interface
39 SYSMON
I2C
PMC_MIO39_SYSMON_I2C_SCLO
40 PMC_MIO40_SYSMON_I2C_SDAI/O
41 PMC_MIO41_SYSMON_I2C_ALERTI/O
42 UART PMC_MIO42_501_RX_IN I
43 PMC_MIO43_501_TX_OUTO
44 I2C1 PMC_MIO44_501_LP_I2C1_SCLO
45 PMC_MIO45_501_LP_I2C1_SDAO
46 I2C0 PMC_MIO46_501_I2C0_SCLI/O
47 PMC_MIO47_501_I2C0_SDAI/O
48 GEM0 PMC_MIO48_GEM_RST_BO
49 Regulator
Enable
GPIO
PMC_MIO49_VCC_PSLP_ENO See Table 1
50 PCIe PMC_MIO50_PCIE_WAKE_BO
51 SD PMC_MIO51_SD_BUSPWRO
502 0 GEM0 LPD_MIO0_GEM_TX_CLK O
1 LPD_MIO1_GEM_TX_D0 I/O
2 LPD_MIO2_GEM_TX_D1 I/O
3 LPD_MIO3_GEM_TX_D2 I/O
4 LPD_MIO4_GEM_TX_D3 I/O
5 LPD_MIO5_GEM_TX_CTL I/O
6 LPD_MIO6_GEM_RX_CLK I
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