AOpen MX4GVR - Page 6

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CNR (Communication and Networking Riser)................................................................................................................ 93
CODEC (Coding and Decoding) .................................................................................................................................... 93
DDR (Double Data Rated) SDRAM ............................................................................................................................... 93
DIMM (Dual In Line Memory Module) ............................................................................................................................ 93
DMA (Direct Memory Access)........................................................................................................................................ 94
ECC (Error Checking and Correction) ........................................................................................................................... 94
EDO (Extended Data Output) Memory .......................................................................................................................... 94
EEPROM (Electronic Erasable Programmable ROM).................................................................................................... 94
EPROM (Erasable Programmable ROM)....................................................................................................................... 94
EV6 Bus ........................................................................................................................................................................ 95
FCC DoC (Declaration of Conformity) ........................................................................................................................... 95
FC-PGA (Flip Chip-Pin Grid Array) ................................................................................................................................ 95
Flash ROM .................................................................................................................................................................... 95
FSB (Front Side Bus) Clock .......................................................................................................................................... 96
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C Bus .......................................................................................................................................................................... 96
IEEE 1394..................................................................................................................................................................... 96
Parity Bit ....................................................................................................................................................................... 96
PBSRAM (Pipelined Burst SRAM)................................................................................................................................. 97
PC-100 DIMM ............................................................................................................................................................... 97