VIPER Power and power management
Before putting the PXA255 into sleep mode, ensure that the R_DIS bit in the ICR
register located at offset 0x100002 from CS5 (0x14100000) is set to ‘1’. The PXA255 is
not designed to interface to 8-bit peripherals, so only the least significant byte from the
word contains the data.
Interrupt configuration and reset register
Byte lane Most Significant Byte Least Significant Byte
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field - - - - - - - - - - - - -
R_DIS
AUTO
CLR
RETRIG
Reset X X X X X X X X 0 0 0 0 0 0 0 0
R/W - - - - - - - - W
Address 0x14100002
ICR bit functions
Bit Name Value Function
0 No interrupt retrigger (embedded Linux/VxWorks)
0 RETRIG
1 Interrupt retrigger (Windows CE .NET)
0 No auto clear interrupt / toggle GPIO1 on new interrupt
1 AUTO_CLR
1 Auto clear interrupt / low pulse for 1.12µS on GPIO1 on
new interrupt
0
2 R_DIS
1
Keep set as 0 under normal operating conditions.
3 - 7 - X No function
© 2004 Arcom Issue H 56
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