ARM DSTREAM-ST - Figure 1-2 Chained JTAG Connection; JTAG Timing Characteristics

The flexible design of the JTAG interface enables you to connect multiple devices to a single debug unit:
Target
Device
Debug
Unit
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
Target
Device
TDI
TMS
TCK
TDO
Figure 1-2 Chained JTAG connection
A group of JTAG devices that are linked or daisy-chained together is often known as the JTAG chain or
scan-chain.
Warning
When multiple devices are used in a scan-chain, the TCK and TMS signals must be branched to each
device. Good digital design practice must be used to ensure that these branches do not reduce the signal
integrity of the signals causing false edges to be received by the devices.
For more information, see JTAG port buffering on page 3-51.
JTAG timing characteristics
The JTAG timing characteristics of DSTREAM-ST conform to the requirements of the IEEE 1149.1
(JTAG) specification.
TDI and TMS are set up by DSTREAM-ST on the falling edge of TCK. These signals are then sampled
by the target device on the rising edge of TCK. The target device must set up its TDO signal when it
detects the falling edge of TCK which, in turn, will be sampled by DSTREAM-ST on the next rising
edge of TCK.
These timings are considered correct at the debug connector of the target board.
Basic JTAG timing:
1 Debug and trace interface
1.1 JTAG signals
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