ARM DSTREAM-ST - Figure 1-15 Trace Signals; Figure 1-16 VTREF Signals

Trace signals
The trace signals (TRACEDATA[0-3] and TRACECLK) are similar to standard inputs, but are also
terminated to VTREF/2 through 50Ω resistors. These resistors prevent signals from being reflected back
to the target system, increasing signal integrity and the maximum data rate.
Disabling the input terminations is not currently supported in Arm Development Studio.
33R
50R
VTREF/2
VTREF/2
Figure 1-15 Trace signals
VTREF signals
The VTREF signals (VTREF, DEBUG_VTREF and TRACE_VTREF) are buffered to provide:
• A VDD rail for the LVCMOS output buffers.
• The VTREF/2 reference/termination rail.
For the debug unit to detect that a target is present, the VTREF signal must higher than 800mV.
33R
10K
5K
5K
Target Detect
Buffered VTREF
VTREF/2
800mV
Figure 1-16 VTREF signals
1 Debug and trace interface
1.8 I/O diagrams for DSTREAM-ST signals
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