ARM DSTREAM-ST - Target Voltage Reference (VTREF) signals

1.7 Target Voltage Reference (VTREF) signals
The Target Voltage Reference, or VTREF, signals are used by DSTREAM-ST to determine the correct
logic levels of all inputs and outputs of the debug and trace interface.
To work with debug and trace interfaces on differing voltage rails, the DSTREAM-ST unit supports
separate debug and trace voltage domains.
VTREF
When using either the CoreSight 20 or Arm JTAG 20 connector, only one voltage domain is supported.
The voltage domain is determined using the VTREF signal.
DEBUG_VTREF
When using the Mictor adapter, or optional MIPI-34 or MIPI-60 adapters, the voltage domain of the
debug signals is determined using the DEBUG_VTREF signal.
TRACE_VTREF
When using the Mictor adapter, or optional MIPI-34 or MIPI-60 adapters, the voltage domain of the trace
signals is determined using the TRACE_VTREF signal.
Note
If only the TRACE_VTREF signal is connected on a Mictor, MIPI-34, or MIPI-60 connector of a
target, DSTREAM-ST uses that signal to determine the logic levels of both the debug and trace signals.
Arm recommends connecting VTREF signals directly to one or more appropriate power rails on the
target board. If a series resistor is used for short-circuit protection, the value used must be less than
100Ω.
VTREF signals that are received by DSTREAM-ST are loaded with a resistance of approximately 10K
to ground. The signals are filtered, limited, and buffered to provide the required VDD (Voh) and
reference voltages (Vi(th)) for the I/O stages of the debug unit.
The DSTREAM-ST unit supports debug and trace logic levels between 1.2V and 3.3V.
Note
• To be recognized by DSTREAM-ST as a valid target reference voltage, VTREF signals must be
above 800mV.
• Logic levels outside the 1.2V to 3.3V window might work, but are not guaranteed to work because
the DSTREAM-ST unit internally limits the VTREF signal to a minimum of approximately 1.1V,
and a maximum of approximately 3.4V.
The relationships of Voh and Vi(th) to VTREF are:
0.0
1.0
2.0
3.0
0.0 1.0 2.0 3.0 4.0
Voh
Vin(th)
VTREF (V)
Voh/Vin(th) (V)
Figure 1-11 Target interface logic levels
1 Debug and trace interface
1.7 Target Voltage Reference (VTREF) signals
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