ARM DSTREAM-ST - Serial Wire Debug (SWD) signals

1.5 Serial Wire Debug (SWD) signals
Serial Wire Debug (SWD) is commonly used on reduced pin-count target devices. SWD only requires
two pins, instead of the four pins used by JTAG.
Serial Wire Data I/O (SWDIO)
During debugging, the Serial Wire Data I/O (SWDIO) signal is bidirectional. It can send and receive
serial data from the target.
The SWDIO signal must be pulled HIGH on the target to keep the signal inactive when no debug unit is
connected.
Warning
SWDIO signal is bidirectional and the functionality is shared with a unidirectional JTAG TMS signal.
Ensure that there are no buffers on the target which would prevent bidirectional communication.
Serial Wire Clock (SWCLK)
During debugging, the Serial Wire Clock (SWCLK) signal is an input to the target which clocks data
into, and out of, the target device.
The SWCLK signal must be pulled LOW on the target to keep the signal inactive when no debug unit is
connected.
Serial Wire Output (SWO)
The Serial Wire Output (SWO) signal is an output from the target which is often used alongside the
SWD signals to provide low-bandwidth trace.
The SWO signal must be pulled HIGH on the target to keep the signal inactive when no debug unit is
connected.
SWD timing requirements
The diagrams that are shown in the following figure separate the SWDIO line to show when it is driven
by either the debug unit or target device:
Tri-StateStop Park
Tri-State Acknowledge Tri-State
Tri-StateStop Park
DataTri-State Acknowledge Data Tri-StateParity
Start
StartData Data Parity
T
ih
T
is
Debug unit output to
SWDIO
Debug unit output to
SWCLK
Target output to SWDIO
Debug unit output to
SWDIO
Debug unit output to
SWCLK
Target output to SWDIO
T
os
T
high
T
low
Read Cycle
Write Cycle
Figure 1-9 SWD timing diagrams
The debug unit:
• Writes data to SWDIO on the falling edge of SWCLK.
• Reads data from SWDIO on the rising edge of SWCLK.
1 Debug and trace interface
1.5 Serial Wire Debug (SWD) signals
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