ASROCK AMD A620 Series - Page 60

56
TSME
Allows you to congure TSME setting.
Conguration options: [Auto] [Disabled] [Enabled]
Data Scramble
Allows you to congure Data Scramble setting.
Conguration options: [Auto] [Disabled] [Enabled]
DDR Addressing Options
Press [Enter] to congure DDR Addressing Options.
Chipselect Interleaving
Interleaves memory blocks across the DRAM chip selected for node 0.
Conguration options: [Auto] [Disabled]
Address Hash Bank
Allows you to enable or disable bank address hashing.
Conguration options: [Auto] [Disabled] [Enabled]
Address Hash CS
Allows you to enable or disable CS address hashing.
Conguration options: [Auto] [Disabled] [Enabled]
BankSwapMode
Allows you to congure BankSwapMode.
Conguration options: [Auto] [Disabled] [Swap APU]
DDR Training Options
Press [Enter] to congure DDR Training Options.
DFE Read Training
e item performs 2D Read Training with DFE on.
Conguration options: [Auto] [Disabled] [Enabled]
DRAM PDA Enumerate ID Programming Mode
Allows you to congure DRAM PDA Enumerate ID Programming Mode.
Configuration options: [Auto] [Sequential PDA enumeration mode] [Legacy PDA
enumeration mode]
DDR Memory MBIST
Press [Enter] to congure DDR Memory MBIST.
MBIST Enable
Allows you to enable or disable Memory MBIST.
Conguration options: [Auto] [Disabled] [Enabled]