168
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
19. SPI – Serial Peripheral Interface
19.1 Features
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
19.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega48A/PA/88A/PA/168A/PA/328/P and peripheral devices or between several AVR
devices.
The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 206. The
PRSPI bit in ”Minimizing Power Consumption” on page 43 must be written to zero to enable SPI
module.
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