AXIOMTEK SBC82621 - Advanced Chipset Features

SBC82621 Socket370 Half-size All-in-One CPU Card User’s Manual
4.2.3 Advanced Chipset Features
This Setup menu controls the configuration of the motherboard
chipset.
CMOS Setup Utility-Copyright © 1984-2001 Award Software
Advanced Chipset Features
DRAM Timing By SPD Enabled Item Help
DRAM Clock Host CLK
SDRAM Cycle Length 3 Menu Level 
Bank Interleave Disabled Enabled adds a
Memory Hole Disabled Parity check to the
P2C/C2P Concurrency Enabled boot-up memory
System BIOS Cacheable Disabled tests. Select
Video RAM Cacheable Disabled Enabled only if the
AGP Aperture Size 64MB system DRAM
AGP Driving Control Auto Contains parity
AGP Driving Value DA
AGP Fast Write Disabled
OnChip USB Enabled
USB Keyboard Support Disabled
CPU to PCI Write Buffer Enabled
PCI Dynamic Bursting Enabled
PCI Master 0 WS Write Enabled
PCI Delay Transaction Enabled
PCI#2 Access #1 Retry Enabled
AGP Master 1 WS Write Disabled
AGP Master 1 WS Read Disabled
Memory Parity/ECC Check Disabled
 : Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
Award BIOS Utility
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