BASF 6106 - Erase Delay Logic

2.2.9.3 ERASE DELAY LOGIC
ERASENAI is always switched a certain delay
time
after WRITE GATE/. The value of the erase
current
is determined by the value of the re-
sistor R67. The delay of the erase current is
necessary. because the tunnel erase gaps are
physically located behind the read/write gap.
This causes the erase
gap to re ach the same
place on the track later than the read/write
gap. Fig. 2-32
shows the erase delay logic.
Fig. 2-33
is a timing diagram for the erase
delay
logic.
FIW~I
IlC-CO\TROL
WRTENA I
PWRONRESETI
A
ERASE OFF
DELAY
ERASE ON
DELAY
A
WRTEN,\ /
ERASE/- FF
A
FIGURE 2 - 32 ERASE DELAY LOGIC
I\'IUTE ENABLE
[RASE ON J)LY
ERASE E:-JABLE
ERASE OFf' 1ll.Y
(320-400) ,",sec
I"'
FIGURE 2 - 33 fRASE OELAY TIMING
2 - 24
El{i\S[K,\ I