Casio CZ-1 - Reset

23. RESET
CIRCUIT
The
following circuit is
Reset
(power
fail
detection)
circuit
which
generates
power
ON/OFF
reset
pulse for
peripheral LSIs
(CPUs, Music
LSIs,
Key
interface
LSI,
and
Key touch
control
LSI),
to
protect
recorded
data
in
the
RAM's.
p—
CE2
for
Main RAM
(j<PD4464C-15L)
RESET
signal
for
Peripheral
LSIs
^
CE2
for Sub
RAM 0iPD4464C-15L
1)
1
—
Timing pulse
for
Flip/Flop
of
key
touch
data
transmission
CE
for
RAM
cartridge
RA-6
CET
for
Sub
RAM
(jiPD4464C 15L-2)