Casio CZ-1 - Block Diagram

5. BLOCK
DIAGRAM
OUT
THRU
H
Main
ROM
*iPD27C256C
20A154
32Kbytt
Main
RAM
jiPD4464C-
15L
2.47MHI
f
8K bytt
VBR(3V)
Kty
touch
control
LSI
MSM6200GS-
1L
CPU.
RAM
tic
I
up/
down detection
circuit
Kty
inttrfact
LSI
#iPD8049HC
•672
MIDI
Inttrfact
LCD unit
__J
|
LED
drive
circuit
MAIN-CPU
j»°D7810H
ADC
;
!
AOC
8.96
MHf
After
MIDI
clock
2MHz
Kg)
15MHI
CPU
inttrfact
LSI
MB64H173
SUB-CPU
jiPD7810H
Sub ROM
0PD23C128EC
-036
16X
bytt
Sub
RAM
(1)
HPD4464C-15L-1
VBRC3V)
BKbVtt
15MHi
Pitch bender
&
Moduration
[8.96
'
MHx
1!
1
Sub
RAM
(2)
JIP04464C-1SL-2
f
8K
bytt
VBRI3V)
Music
LSI
Music
LSI
(Masttr)
(Slave)
jrf>D933AC-1
|rf>D933AC-2
Power
source
circuit
*
av
,
VDL1.VDL2
,
15V
(WCCI
-15V
C-VCC)
Lint-out
(R)
(A/A*B>
Linrout(L)
(B)
-16-