Casio CZ-1 - Cpu Interface Lsi (Mb64 H173)

8.
MAIN
RAM
&
ROM
ACCESSES
P07
t
POO
RO
PF7
I
PFO
MAIN-CPU
MPO7810H
AL6
C
Data
bus
07-00
'
•
•
»
1Y2
1/08-1/01
OE
WR
CE1
Main RAM
/JPD4464C-16L
A11~A8
A7~A0
£E2
Decoder
SN74LS139M
1
A, 18,10
00-07
OE
Main
ROM
UPD27C256C-20A154
A14~A8
gg
A7-A0
Address but
A15
-
A8
CPU
interface
810
LSI
OLOO
I
I
817
OL07
MB74H178
I
LOG
Addrtss
bus
A7
-
AO
A1S-A13
^Normal
HIGH
(aval
Rasat
circuit
'LSI
39
(EACH
OECOOER/OEMULTIPLEXER)
FUNCTION
TA8L8
INPUTS
OUTPUTS
ENABLE
G
SELECT
8
A
YO Y1
Y2
Y3
H
X X
H H
M
H
L
L
L
L
H H
H
L
L
H H
L
M M
L
H
L
H M
L M
L
H H H
M M
L
8K bytt
of
Main
RAM
is tht data
ansa as
writttn
on page
17.
Tha
RAM is
backed up
by +VBR
(3V) of
lithium battery.
Tha
capacity of
Main
ROM
is
32K
byta
and containts program
for the
system execution.
Lower
address bus
(AO
-
A7)
is
provided from CPU
interface
LSI
(MB74H178).
When signal
ALE
from
Main
CPU
rises
to
HIGH, data bus
(DO
-
07)
becomes address bus
(AO
~
A7)
in
CPU
interface
LSI
(MB74H178).
Upper
address bus
A8
-
A15
is directly
supplied from
Main
CPU.
Chip select
signals are
from signals
A13
-
A15.
Chip
selection A13
AM A16
WR re
Main RAM
LOW LOW HIGH
Hor
L
HIGH
Main ROM
LOW
LOW
-21-