Casio CZ-1 - Page 89

(4)
Key
and switch
scanning
Receiving
a
key
common signal
from
data bus,
MAIN
CPU
discriminates
a
key
or
a
switch
input.
From
signals PAO
-
PA3
of MAIN
CPU,
4-line
to
16-line
decoder 74LS154P-2
generates
key common
signals
KCO
-
KC1
1
.
When
a
switch is
put,
one of the
input signals
KIO
-
KI5
(for switches)
is entered in
CPU
Interface
LSI
MB64H173.
MAIN
CPU
generates
the clock pulse
'4'
(for
switches), causing
the tristate buffers
to
be
opened.
The input pulse
is
entered into
data bus.
Discriminating the
contents
of the
data bus. MAIN
CPU
determines which switch
is
pushed.
INPUT
OUTPUT
-G1
_G2
D C
-JL._A.
1
2 .3™
.
1 &
fi
-J . a
a 10
U
12 -12.
.12
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74LS1S4P Function
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