Casio CZ-1 - Page 97

12.
DATA
CLOCK
PULSE
GENERATOR
Addrtu
latch
for
RAM
pack
SN74LS174N-3
CUR
CLR
Data
latch
for
tttrao
circuit
SN74LS174N2
Addrass
latch
for RAM
pack
SN74LS374N
CLIC
LEO
drivt
circuit
From
SUB
CPU
c
PR
LS74
CK
SN74LS154P1
n
16
17
-#18
16
1*
1C
10
Kty
inttrfaca
LSI
4iP08048HC-e72
10
-H7 P77 TO
f
Flip/Flop
r
LS74
»«|PR
CK
CLR
Y6
Y7
I
Y11
Y14
Y1S
Y12
Y13
s
s
u
I
A
B
c
D
01
G2
AO
A1
A3
-a-
A3
35
WR
(Normal
HIGH lavri)
Buffer
SN74LS340
1CM-
2Qm-
Rtttt
Circuit
OGNIG1
IG2
3
PCS
A14
A1S
00
I
07
MAIN
CPU
UPO7810H
MB64H173
CPU
inttrfaca LSI
Oatabut
00-07
Tarmuta!
Clock
Function
VB
#16
Clock
pulsa
for
imarrupt
from
Sub
CPU to
Main
CPU.
V7-Y11
#17-018 Clock
pulia
for
LEO
drivt
circuit.
ria
ic
Clock
pulit of control signal
for
ttarao circuit.
Y1J
#10
Enabla signal of
buffar
(SN74LS240N)
and
rasat pulsa
of Flip/Flop
(SN74LS74) for
kty
data
transmission.
V14.Y1B
1E.01F
ALE
(Addrass
Latch Enabla)
signal
for
RAM pack.
-36-