Chroma 63206 - Output Queue; Standard Event Status

Status Reporting
OP
2 4
Overpower. An overpower condition has occurred on a channel,
Bit 2 is set and remains set until the overpower condition is
removed and LOAD:PROT:CLE is programmed.
RV
3
8
Reverse voltage on input. When a channel has a reverse voltage
applied to it, Bit 3 is set. It remains set until the reverse voltage is
removed and LOAD:PROT:CLE is programmed.
OT
4
16
Over temperature. When over temperature condition has occurred
on a channel, Bit 4 is set and the channel is turned off. It remains
set until the channel has cooled down well below the over
temperature trip point and LOAD:PROT:CLE is programmed.
LD
5
32
Load on. Once any channel goes to
“Load On” condition, the bit
will be set until
“Load On” disappears in all channels.
ST
6
64
Short on. Once any channel goes to
“Short On” condition, the bit
will be set until “Short On” disappears in all channels.
PF
7
128
SPEC TEST pass/fail indicator. Under
“SPEC TEST On”
condition, “1” represents SPEC TEST pass, “0” represents SPEC
TEST fail.
SP
8
256
SPEC TEST on. As long as specification checking function is
enabled, the bit will be set. Otherwise, the bit is reset.
FF
12
4096
Fan fail. “Fan Fail” means that the fan on any module is out of
order. Once the condition happens, “1” will reflect on the bit.
Users can program “LOAD:PROT:CLE” to clear the condition. If
the fan doesn’t function well after programming the command,
the bit will still be set in seconds.
RS
13
8192
Remote Sensing Connection. Once Vsense terminals are connected
to UUT, the bit is set until the connection disjoined.
PR
14
16384
Program run. When a program is running, the bit is set and
remains set until the program comes to an end.
Table 8-1 Bit Description of Questionable Status
8.4 Output Queue
 The Output Queue stores output messages until they are read from the electronic load.
 The Output Queue stores messages sequentially on a FIFO (First-In, First-Out) basis.
 When there is data in the queue, it sets it to 4 (MAV bit) in the Status Byte register.
8.5 Standard Event Status
 All programming errors that have occurred will set one or more of the error bits in the
Standard Event Status register. Table 8-2 describes the standard events that apply to
the electronic load.
8-3