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Clevo N240BU - Processor 2;11

Clevo N240BU
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Schematic Diagrams
B - 4 Processor 2/11
B.Schematic Diagrams
Processor 2/11
Sheet 3 of 41
Processor 2/11
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1:2 (4mils:8mils)
6-17-10300-730
Analog Thermal Sensor
EVT
⼴䴻
Thermal
⼙⁷
⁷䅙
䅙䚠
䚠₨
₨䡢
䡢⭂
PCB
㚨檀
檀㹓
㹓⹎
, NTC
ㅱ娚
娚㓦
㓦伖
PCB
㚨檀
檀㹓
㹓⹎
⹎嗽
.
Max < 600MILS, W=5MILS, SPACE=25MILS
10K_1%_NTC_04
4/29
5/6
CSI2_COMP
EMMC_RCOMP
EDP_RCOMP
SMI#_R
SCI#_R
VGA_CTRLDATA
VGA_CTRLCLK
EMMC_CMD
EMMC_RCLK
EMMC_CLOCK
EMMC_DATA2
EMMC_DATA1
EMMC_DATA7
EMMC_DATA6
EMMC_DATA5
EMMC_DATA3
EMMC_DATA0
EMMC_DATA4
PCH_GPP_D4
VGA_AUX_CH_N
SCI#_R
SMI#_R
VGA_AUX_CH_P
HDMI_CTRLCLK
HDMI_CTRLDATA
HDMI_AUXN
HDMI_AUXP
EDP_HPD
3.3V
VCCIO_OUT
3.3VS
3.3VS
3.3VS
EDP_TXN_0 16,18
EDP_TXP_0 16,18
EDP_TXN_1 16,18
EDP_TXP_1 16,18
EDP_AUXP 16,18
EDP_AUXN 16,18
NB_ENAVDD 16
EDP_BRIGHTNESS 18
BLON_N 16
THERM_VOLT 25
SMI# 25
SCI# 25
HDMI_DATA1N15
HDMI_DATA1P15
HDMI_DATA2N15
HDMI_DATA2P15
HDMI_CLOCKN15
HDMI_CLOCKP15
HDMI_DATA0N15
HDMI_DATA0P15
VGA_LANE0N17
VGA_LANE0P17
VGA_LANE1N17
VGA_LANE1P17
HDMI_CTRLCLK15
HDMI_CTRLDATA15
VGA_AUX_CH_P 17
VGA_AUX_CH_N 17
EDP_HPD 16,18
HDMI_HPD 15
VCCIO_OUT9,31
3.3VS4,5,6,7,13,14,15,16,17,18,19,20,22,23,24,25,26,27,32
3.3V6,7,16,19,20,21,22,26,27,29,31
VGA_HPD 17
Title
Size Document Number Rev
Date: Sheet
of
6-71-N24J0-DB2
1.0
[03] KBL 2/11 DISPLAY
A4
342Tuesday, June 28, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N240BU
Title
Size Document Number Rev
Date: Sheet
of
6-71-N24J0-DB2
1.0
[03] KBL 2/11 DISPLAY
A4
342Tuesday, June 28, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N240BU
Title
Size Document Number Rev
Date: Sheet
of
6-71-N24J0-DB2
1.0
[03] KBL 2/11 DISPLAY
A4
342Tuesday, June 28, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N240BU
SKL_ULT
CSI-2
EMMC
9 OF 20
REV = 1
U19I
SKL_ULT
CSI2_DN0
A36
CSI2_DP0
B36
CSI2_DN1
C38
CSI2_DP1
D38
CSI2_DN2
C36
CSI2_DP2
D36
CSI2_DN3
A38
CSI2_DP3
B38
CSI2_DN4
C31
CSI2_DP4
D31
CSI2_DN5
C33
CSI2_DP5
D33
CSI2_DN6
A31
CSI2_DP6
B31
CSI2_DN7
A33
CSI2_DP7
B33
CSI2_DN8
A29
CSI2_DP8
B29
CSI2_DN9
C28
CSI2_DP9
D28
CSI2_DN10
A27
CSI2_DP10
B27
CSI2_DN11
C27
CSI2_DP11
D27
CSI2_CLKN0
C37
CSI2_CLKP0
D37
CSI2_CLKN1
C32
CSI2_CLKP1
D32
CSI2_CLKN2
C29
CSI2_CLKP2
D29
CSI2_CLKN3
B26
CSI2_CLKP3
A26
CSI2_COMP
E13
GPP_D4/FLASHTRIG
B7
GPP_F13/EMMC_DATA0
AP2
GPP_F14/EMMC_DATA1
AP1
GPP_F15/EMMC_DATA2
AP3
GPP_F16/EMMC_DATA3
AN3
GPP_F17/EMMC_DATA4
AN1
GPP_F18/EMMC_DATA5
AN2
GPP_F19/EMMC_DATA6
AM4
GPP_F20/EMMC_DATA7
AM1
GPP_F21/EMMC_RCLK
AM2
GPP_F22/EMMC_CLK
AM3
GPP_F12/EMMC_CMD
AP4
EMMC_RCOMP
AT1
R5324.9_1%_04
R52 *10K_04
R692.2K_04
R56 *10K_04
R712.2K_04
R345 100_1%_04
R70 *10mil_04
R4242.2K_04
R652.2K_04
R38 100K_04
R74
4.7K_1%_04
R64 10K_04
PTH1
TH05-3H103FR
1 2
SKL_ULT
EDP
DISPLAY SIDEBANDS
DDI
1 OF 20
REV = 1
U19A
SKL_ULT
DDI1_AUXN
G50
DDI1_AUXP
F50
DDI1_TXN[0]
E55
DDI1_TXN[1]
E58
DDI1_TXN[2]
F53
DDI1_TXN[3]
F56
DDI1_TXP[0]
F55
DDI1_TXP[1]
F58
DDI1_TXP[2]
G53
DDI1_TXP[3]
G56
DDI2_AUXN
E48
DDI2_AUXP
F48
DDI2_TXN[0]
C50
DDI2_TXN[1]
C52
DDI2_TXN[2]
A50
DDI2_TXN[3]
D51
DDI2_TXP[0]
D50
DDI2_TXP[1]
D52
DDI2_TXP[2]
B50
DDI2_TXP[3]
C51
DDI3_AUXN
G46
DDI3_AUXP
F46
EDP_RCOMP
E52
EDP_AUXN
E45
EDP_AUXP
F45
EDP_DISP_UTIL
B52
EDP_TXN[0]
C47
EDP_TXN[1]
D46
EDP_TXN[2]
A45
EDP_TXN[3]
A47
EDP_TXP[0]
C46
EDP_TXP[1]
C45
EDP_TXP[2]
B45
EDP_TXP[3]
B47
GPP_E13/DDPB_HPD0
L9
GPP_E14/DDPC_HPD1
L7
GPP_E15/DDPD_HPD2
L6
GPP_E16/DDPE_HPD3
N9
GPP_E17/EDP_HPD
L10
GPP_E18/DDPB_CTRLCLK
L13
GPP_E19/DDPB_CTRLDATA
L12
GPP_E20/DDPC_CTRLCLK
N7
GPP_E21/DDPC_CTRLDATA
N8
GPP_E22/DDPD_CTRLCLK
N11
GPP_E23/DDPD_CTRLDATA
N12
EDP_BKLTCTL
R11
EDP_BKLTEN
R12
EDP_VDDEN
U13
R59 10K_04
R60 *10mil_04
R1868 200_1%_04

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