5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TLS Confidentiality
LOW = Disable Intel ME
Crypto TLS (Default)
GPP_C2
HIGH =Enable Intel ME
Crypto TLS
STRAP PIN
eSPI or LPC
LOW = LPC Is selected for EC
(Default)
GPP_C5
HIGH=eSPI Is selected for EC
PCH_GPP_D21
TPM Type Detect
HIGH = TPM
3.3V_SPI
SPI_* = 1.5"~6.5"
BIOS+ME ROM
64Mbit
Co_Lay
婳㬋側䔲
⤪
COST DOWN
⎗䚩䔍
㗗⏎⎗䚜㍍
SHORT
layout
⼴䚜㍍
short
3.3VA
3.3VS
3.3VS
3.3V_SPIVDD3
3.3VS
3.3V_SPI
CL_RST#119
CL_CLK119
CL_DATA119
SMB_CLK 24
SMB_DATA 24
PM_CLKRUN# 18
PCLK_TPM 18
PCLK_KBC 26
SERIRQ18,26
SB_KBCRST#26
HSPI_SCLK26
HSPI_CE#26
HSPI_MSI26
HSPI_MSO26
ASM1142_SMI#21
3.3V_SPI10
VDD34,6,7,10,17,19,22,24,26,27,28,29,30,32,33
3.3VA6,7,8,10,26,27
3.3VS2,4,6,7,8,13,14,15,16,17,18,19,20,21,24,25,26,27,31
LPC_FRAME# 18,26
LPC_AD0 18,26
LPC_AD1 18,26
LPC_AD2 18,26
LPC_AD3 18,26
SMB_CLK_DDR 13,14
SMB_DAT_DDR 13,14
Title
Size Document Number Rev
Date: Sheet
of
2.0
[05] KBL U LPC,SPI,SMB
A3
540W ednesday, August 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N7505-001
6-71-N7500-D02
Title
Size Document Number Rev
Date: Sheet
of
2.0
[05] KBL U LPC,SPI,SMB
A3
540W ednesday, August 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N7505-001
6-71-N7500-D02
Title
Size Document Number Rev
Date: Sheet
of
2.0
[05] KBL U LPC,SPI,SMB
A3
540W ednesday, August 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N7505-001
6-71-N7500-D02
R433 15_1%_04
R411 *1K_04
R407 *499_1%_04
R70*10mil_Short_04
R369 10K_04
R410 *1K_04
R432 15_1%_04
R448 22_04TPM
R459 10K_04
R106*10mil_Short_04
R408 *499_1%_04
R427 15_1%_04
R443 *10mil_Short_04
R434
1K_1%_04
R399 10K_04TPM
R327 *30mil_short_06
R401 10K_04W/O TPM
R415
1K_1%_04
R436*10mil_Short_04
R96 *10K_04
R413*10mil_Short_04
R409 *10K_04
R403 1K_04
R414*10mil_Short_04
R390
2.2K_04
U23
GD25B64CSIGR
PCB Footprint = ACA-SPI-004-T03
CE#
1
SO
2
WP#
3
VSS
4
SI
5
SCK
6
HOLD#
7
VDD
8
R435*10mil_Short_04
R65 2.2K_04
R402 1K_04
R391
2.2K_04
R107*10mil_Short_04
R447 10K_04
S
D
G
Q14A
MTDK5S6R
2
6 1
C436
0.1u_16V_Y5V_04
S
D
G
Q14B
MTDK5S6R
5
3 4
R428 15_1%_04
R461 8.2K_04
R71*10mil_Short_04
R429 15_1%_04
KBL_ULT
SPI - FLASH
SMBUS, SMLINK
SPI - TOUCH
C LINK
LPC
5 OF 20
REV = 1
U1E
KBL_ULT/BGA
SPI0_CLK
AV2
SPI0_MISO
AW3
SPI0_MOSI
AV3
SPI0_IO2
AW2
SPI0_IO3
AU4
SPI0_CS0#
AU3
SPI0_CS1#
AU2
SPI0_CS2#
AU1
GPP_D1/SPI1_CLK
M2
GPP_D2/SPI1_MISO
M3
GPP_D3/SPI1_MOSI
J4
GPP_D21/SPI1_IO2
V1
GPP_D22/SPI1_IO3
V2
GPP_D0/SPI1_CS#
M1
CL_CLK
G3
CL_DATA
G2
CL_RST#
G1
GPP_A0/RCIN#
AW13
GPP_A6/SERIRQ
AY11
GPP_C0/SMBCLK
R7
GPP_C1/SMBDATA
R8
GPP_C2/SMBALERT#
R10
GPP_C3/SML0CLK
R9
GPP_C4/SML0DATA
W2
GPP_C5/SML0ALERT#
W1
GPP_C6/SML1CLK
W3
GPP_C7/SML1DATA
V3
GPP_B23/SML1ALERT#/PCHHOT#
AM7
GPP_A1/LAD0/ESPI_IO0
AY13
GPP_A2/LAD1/ESPI_IO1
BA13
GPP_A3/LAD2/ESPI_IO2
BB13
GPP_A4/LAD3/ESPI_IO3
AY12
GPP_A5/LFRAME#/ESPI_CS#
BA12
GPP_A14/SUS_STAT#/ESPI_RESET#
BA11
GPP_A9/CLKOUT_LPC0/ESPI_CLK
AW9
GPP_A10/CLKOUT_LPC1
AY9
GPP_A8/CLKRUN#
AW11
R444 22_04
CL_RST#1
PCH_GPP_C2
SML0CLK
SML0DATA
SML1DATA
SML1CLK
CL_CLK1
CL_DATA1
SPI_SCLK_R
SPI_CS_0#
SPI_SI_R
SPI_SO_R
PCH_SPI_DQ2
PCH_SPI_DQ3
PCH_GPP_B23
SMB_CLK
SMB_DATA
PCH_GPP_C5
SML1DATA
SML1CLK
SML0DATA
SML0CLK
PCH_GPP_C2
PM_CLKRUN#
PM_CLKRUN#
LPC_1
LPC_0
SERIRQ
SERIRQ
SB_KBCRST#_R
SB_KBCRST#_R
TPM_DET#
SMB_DATA
SMB_CLK
SPI_SI_M
SPI_WP#_0
SPI_HOLD#_0
SPI_CS0#
SPI_SO_M
SPI_SCLK_M
SPI_SI
SPI_SCLK_M
SPI_CS0#
SPI_SO
SPI_SCLK
SPI_SI_M
SPI_SO_M
SPI_CS_0#
SPI_HOLD#_0
SPI_WP#_0
SPI_SCLK
SPI_SO
SPI_SI
ASM1142_SMI#
SMB_DATA
SMB_CLK
PCH_GPP_C5
PCH_GPP_B23
S4_STATE#
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