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Clevo N950TP6 - Pex_Vdd

Clevo N950TP6
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Schematic Diagrams
B - 62 PEX_VDD
B.Schematic Diagrams
PEX_VDD
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
POWER RAIL State in GC6
1V8_AON
1V8_MAIN
PEX&1.05V
NVVDD
ON
OFF
OFF
OFF
Dpme!cppu0Pqujnvt;!2W9`BPOʈ2W9`SVOʈOWWEEʈOWWEET!ʈQFY`WEEʈGCWEER
HD7!3/2!Fyju;!2W9`SVOʈOWWEE`MʈOWWEE`TʈQFY`WEE!ps!2W9`SVOʈOWWEE`MʈOWWEE`T!'!QFY`WEE
GC6 2.1 Control Signals
1.1V8_MAIN_EN
2.GC6_FB_EN
3.GPU_EVENT#
4.GPU_PEX_RST_HOLD#
5.SYS_PEX_RST_MON#
GPU
1V8_MAIN_EN
GC6_FB_EN
VR Complex
1V8_AON
1V8_MAIN
NVVDD
PEX&1.05V
NVVDDS
EC/PCH
GPU_PWR_EN
GPU_EVENT#
GPU_RST#
PLATFORM_RST#
SYS_PEX_RST_MON#
GPU_PEX_RST_HOLD#
GPU_PEX_RST#
FBVDD/Q
FBVDD/Q ON
NVVDDS OFF
close to ICPlace resistors
GC6 2.1 - VR Complex
1. GPU_PWR_EN
2. 1V8_MAIN_EN
3. GC6_FB_EN
GPU
GPU_PWR_EN
(SYSTEM)
1V8_AON
1V8_AON
1V8_MAIN_EN 1V8_MAIN
PEX&1.05V
NVVDD
FBVDD/Q
EN
EN
EN
EN
EN
PGOOD
PGOOD PGOOD
PGOOD
GC6_FB_EN
PGOOD
Rt
2.6Amps @ 1.0V
Open VREG Type 0
PEX_VDD
Vout= Vref * (1+(Rt/Rb))
Rb
1.050V= 0.6 * (1+(7.5K/10K))
DG P.93 note: t1(from 1V8_RUN_EN to PEX_VDD/NVVDD_PG) must NOT exceed 4ms.
N17E
FBVDDQ
POWER ON SEQUENCE POWER OFF SEQUENCE
GPPG0_PCH_PEXVDD_EN (GPP_G0) (PEX_VDD)
GPPG11_PCH_NVVDDS_EN (GPP_G11) (NVVDDS)
GPPG10_PCH_NVVDD_EN (GPP_G10) (NVVDD)
GPPG9_PCH_NV3V3_EN (GPP_G9) (NV3V3)
GPPG8_PCH_1V8RUN_EN (GPP_G8) (1V8_MAIN)
DGPU_PWR_EN (GPP_F23) (1V8_AON)
net PCH_GPIO Voltage
D02 0511
PWR_SRC_NV
GND
GND
GND
VIN
PWR_SRC_NV _FB
GND
5V
GND
GND
GND
GND
GND
PEX_VDD
GND
3.3V
GND
3.3VS
VDD3
PWR_SRC_NVVDDS
NV3V3
NV3V3
1V8_AON
PWR_SRC_NV _FB
PWR_SRC_NV _FB
GND
GND
GND
GND
FBVDDQ_SENSE_RTN[24,62]
FBVDDQ_SENSE[24,62]
GPU_NVVDD_SENSE[24,59]
GPU_GND_SENSE[24,59]
I2CC_SDA[22,61]
I2CC_SCL[22,61]
I2CC_SDA [22,61]
I2CC_SCL [22,61]
PS1_NVVDD_EN [59]
GPIO28_OC_W ARN# [22]
5V[28,42,43,45,50,53,54,55,56,58,62]
1V8_RUN[10,11,19,20,24,58]
3.3V[2,23,28,29,39,40,41,43,50,51,53,54,58]
VIN[29,33,50,51,52,53,54,55,56,57,59]
VDD3[30,31,33,36,37,40,42,44,45,48,50,51,52,56,57,58,59,60,62]
PWR_SRC_NV _FB[62]
PEX_VDD[10,21]
PWR_SRC_NV[59]
NV3V3[10,22,28,58]
NV_PEXVDD_EN [23]
PWR_SRC_NVVDDS[60]
3.3VS[8,9,23,26,27,28,29,30,32,33,34,35,36,37,40,41,44,45,46,47,48,49,50,54,59,60,62]
1V8_AON[10,19,20,22,23,24,58,59,60,62]
Title
Size Document Number Rev
Date: S heet
of
6-71-N9500-D01A
D01A
[61] PEX_VDD
Custom
61 68Friday, October 06, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: S heet
of
6-71-N9500-D01A
D01A
[61] PEX_VDD
Custom
61 68Friday, October 06, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: S heet
of
6-71-N9500-D01A
D01A
[61] PEX_VDD
Custom
61 68Friday, October 06, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
PR324 7.5K_1%_04
PC227
10u_6.3V_X5R_06
PR330
*10K_04
PR341 10K_04
PJ66*CV-40m il
12
PR344 0_04PR343 10K_04
PC221
1u_6.3V_X5R_04
PR331 665K_1%_04
PR326 *10_1%_04
PR333 10_1%_04
PC224
10u_6.3V_X5R_06
PR336 10_1%_04
PR393
*15_1%_06
PC214
22u_6.3V_X5R_08
PC220
0.1u_10V_X7R_04
PC226
10u_6.3V_X5R_06
PRS5
COMMON
1%
SMDRL1632L4-R005-FNH
1206
1
2 3
4
PR316
10_06
PR335 10K_04
PC215
0.1u_10V_X7R_04
PR317
10K_1%_04
PR332 *0_04
PR323 0_04
PR328 10_1%_04
PR337 10_1%_04
PR321 0_04
PU17
INA3221AIRGV
1
VIN3N
2
VIN3P
3
GND
4
VS
5
A0
6
SCL
7
SDA
8
WARN
9
CRIT
10
PV
11
VIN1N
12
VIN1P
13
TC
14
VIN2N
15
VIN2P
16
VPU
17
PAD
PR334 665K_1%_04
PR338 *0_04
PL17
BCIHP0420TB-2R2M
1 2
PR342 0_04
PR322 *0_04
OpenVReg
PU16
RT8071CGQW
1
FB
2
VCC
3
VIN
4
GND
5
GND
6
SW
7
SW
8
BOOT/NC
9
PGOOD
10
EN/FS
11
THERM
R750
100K_04
PC222 *3300p_50V_X7R_04
PR339 665K_1%_04
PJ67
3mm
1 2
PR340 10_1%_04
PR318 10K_04
PC218
22u_6.3V_X5R_08
PR320 10K_04
PC225
0.01u_16V_X7R_04
PR329 10_1%_04
PRS4
COMMON
1%
SMDRL1632L4-R005-FNH
1206
1
23
4
PRS6
COMMON
1%
SMDRL1632L4-R005-FNH
1206
1
2 3
4
PC219
22u_6.3V_X5R_08
PR319 *165K_1%_04
S
D
G
Q44A
MTDK3S6R
2
61
PR394
15_1%_06
PC217
*0.22u_10V_X5R_04
PR325 10K_1%_04
+
PC223
EEEFZ1E101P
SCAR250-1
S
D
G
Q44B
MTDK3S6R
5
34
PC216 *0.01u_16V_X7R_04
FBVDDQ_SENSE
FBVDDQ_SENSE_RTN
I2CC_SCL
I2CC_SDA
GPU_NVVDD_SENSE
GPU_GND_SENSE
I2CC_SCL
I2CC_SDA
PS1_NVVDD_EN
10A
0.400
PWR_SRC_CRTCA L
PWR_SRC_IM ON_A0
10A
0.400
10A
0.400
PWR_SRC_NV_VINN_R
PWR_SRC_NV_VINP_R
PWR_SRC_VALID
PWR_SRC_VI NNPWR_SRC_VINN_R
PWR_SRC_VINP_R
PWR_SRC_WARN
SNN_TC
SNN_VPU
VIN2N
VIN2P
PWR_SRC_VI NP
PEX_VDD_R
1.1V/1.4A
PS6_FB_MARGIN_PEXVDD
PU16_BOOT
PS6_FB_RR_PEXVDD
PU16_SW
0.200
PEX_VDD_PWRGD
PEXVDD_EN
PEX_VDD_R
10A
0.400
PWR_SRC_NVS_VINN_R
PWR_SRC_NVS_VINNP_R
VIN3N
VIN3P
PEXVDD_EN
Sheet 61 of 68
PEX_VDD

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