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Clevo N950TP6 - Chipset Schematics

Clevo N950TP6
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Sheet 30 of 68
PCH 1/9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RTC Wake UP
For ITE IT8587B Test
ME+BIOS ROM 8MB
BOOT HALT
ENABLE:LOW
(INTERNAL WEAK PD)
CONSENT STRAP
ENABLE:LOW
(INTERNAL WEAK PU)
JTAG ODT
DISABLE:LOW
(INTERNAL WEAK PU)
GPP_G_14_GSXDIN:
DMI AC COUPLING FULL VOLTAGE MODE
WHEN SAMPLED LOW
SPI_* = 1"~6.5"
PESONALITY STRAP
ENABLE:LOW
(INTERNAL WEAK PU)
ESPI FLASH SHARING MODE
MASTER ATTACHED FLASH SHARING:LOW
SLAVE ATTACEHD FLASH SHARING:HIGH
(INTERNAL WEAK PD)
Leakage
Default Short
VCC_RTC
SPI_3.3V
3.3VS
3.3VA
3.3VS
VDD3
HSPI_CE#[48]
HSPI_MSI[48]
HSPI_MSO[48]
HSPI_SCLK[48]
PLT_RST# [23,31,46]
VDD3[31,33,36,37,40,42,44,45,48,50,51,52,56,57,58,59,60,61,62]
3.3VS[8,9,23,26,27,28,29,32,33,34,35,36,37,40,41,44,45,46,47,48,49,50,54,59,60,61,62]
VCC_RTC[33,36]
LAN_WAKEUP#[33,40,44,48]
3.3VA[3,9,31,32,33,36,37,51]
SPI_3.3V[36]
Title
Size Document Number Rev
Date: Sheet
of
6-71-N9500-D01A
D01A
[30] PCH 1/12-SPI/SMBUS
A3
30 68Friday, October 06, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-N9500-D01A
D01A
[30] PCH 1/12-SPI/SMBUS
A3
30 68Friday, October 06, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-N9500-D01A
D01A
[30] PCH 1/12-SPI/SMBUS
A3
30 68Friday, October 06, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
R332
*1K_04
T21
R327
*4.7K_04
T17
R336 *20mil_short_04
T19
U32
MX25L6433F
CE#
1
SO
2
WP#
3
VSS
4
SI
5
SCK
6
HOLD#
7
VDD
8
R338 *20mil_short_04
C631
0.1u_10V_X7R_04
T22
T25
1 OF 13
REV = 1
U31A
KBP_H_PCH_DT_EV_CRB/BGA
SPI0_CLK
BE29
SPI0_MOSI
BF27
SPI0_MISO
BE27
TP1
AP17
GPP_H16/SML4CLK
BD36
GPP_E3/CPU_GP0
AP41
TP2
AU19
GPP_G16/GSXCLK
T43
GPP_D21
AM44
GPP_D0
AV41
GPP_B4/CPU_GP3
BF22
GPP_A11/PME#
BF15
GPP_D22
AM42
GPP_D1
AY39
GPP_D2
BB44
GPP_H17/SML4DATA
BF32
GPP_E7/CPU_GP1
AK43
GPP_D3
AV43
GPP_B3/CPU_GP2
BF21
SPI0_IO2
BF26
GPP_H14/SML3DATA
AV31
GPP_B13/PLTRST#
BD24
SPI0_CS2#
AY27
SPI0_IO3
BD27
GPP_H11/SML2DATA
AU31
GPP_H10/SML2CLK
BE32
GPP_G15/GSXRESET#
U44
SPI0_CS1#
BA27
SPI0_CS0#
BF28
GPP_H18/SML4ALERT#
BF34
RSVD4
AF17
GPP_G13/GSXSLOAD
Y36
RSVD3
AG17
GPP_H15/SML3ALERT#
BD33
RSVD2
AH14
GPP_H13/SML3CLK
BE33
RSVD1
AH16
GPP_H12/SML2ALERT#
BF33
INTRUDER#
BF9
GPP_G14/GSXDIN
Y43
GPP_G12/GSXDOUT
AC39
R340 33_04
PJ2 1mm
12
R343 33_04
R325
*4.7K_04
T16
R337 *20mil_short_04
T18
RN1 *10K_8P4R_04
1
2
3
4 5
6
7
8
R339 33_04
R331
*4.7K_04
R330 1M_04
T26
T20
T23
R333*10K_04
R334
*4.7K_04
R342 0_04
T24
R328 33_04
R335 *20mil_short_04
R341 1K_1%_04
R326
*0_04
R329 33_04
R344 1K_04
SPI_SI_M
SPI_SO_M
SPI_CS0#
SPI_SCLK_M
SPI_WP#
SPI_SI_R
SPI_SO_R
SPI_CS_0#
SPI_SCLK_R
SPI_SI_R
SPI_SO_R
SPI_SCLK_R
SPI_CS_0#
SPI_IO2
SPI_IO3SPI_SO_R
SPI_SI_R
SPI_SO_R
SPI_CS_0#
SPI_SCLK_R
LAN_WUP#
SPI_WP#
SPI_HOLD#
GPP_G_14_GSXDIN
SML4ALERT#
SML4DATA
SML4CLK
SML3ALERT#
SML3CLK
GPP_H_12
SML2DATA
SML2CLK
INTRUDE R#
SML3DATA
GPP_H_12
EXTTS_SNI_DRV0
TCH_PNL_INTR#
EXTTS_SNI_DRV1
SPI_HOLD#
GPP_G16
GPP_G12
HSPI_MSI
HSPI_MSO
HSPI_SCLK
HSPI_CE#
SMI#_R
SPI_IO2
SPI_IO3
SPI_SI_R
Schematic Diagrams
PCH 1/9 B - 31
B.Schematic Diagrams
PCH 1/9

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