5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFL-S Processor 2/6 (JTAG,CLK,CFG )
CPU_24MHZ
DESIGN NOTE:
DESIGN NOTE:
CFG[4]
1:Disabled - No Physical Display Port
attached to Embedded DisplayPort*.
No connect for disable.
0:Enabled - A Display Port device is
connected to the Embedded Display Port.
Pull-down to GND through a 1 K? ±5%
resistor to enable port.
DESIGN NOTE:
CFG[6:5]
00 = 1x8, 2x4 PCI Express* 01 = reserved
10 = 2x8 PCI Express* 11 = 1x16 PCI Express*
Recommend 1K ? ±5% pull-down resistor to GND.
PU/PD for JTAG signals
DESIGN NOTE:
CFG[7]
1 = (default) PEG train immediately following
RESET# de assertion.
0 = PEG wait BIOS for training.
CAD Note: Capacitor need to be placed
close to buffer output pin
3.3Vx(2.74K/(6.04K+2.74K))=1.029V
VCCST_VCCPLL
3.3VA
VCCST_VCCPLL
VCCST_VCCPLL
VCCST_VCCPLL[6,33,51,54]
H_PECI[48]
PCH_THERMTRIP#[32]
H_PM_SYNC[32]
H_VIDALERT#_VR[54]
H_VIDSCK_VR[54]
H_VIDSOUT_VR[54]
PCH_CPU_BCLK_R_DP[35]
PCH_CPU_BCLK_R_DN[35]
PCH_CPU_PCIBCLK_R_DP[35]
PCH_CPU_PCIBCLK_R_DN[35]
CPU_24MHZ_R_DP[35]
CPU_24MHZ_R_DN[35]
PM_PCH_PWROK[9,31,33]
H_PWRGD[33]
PLTRST_CPU#[32]
H_PM_DOWN[32]
H_SKTOCC#[34]
H_PROCHOT_EC[48]
3.3VA[9,30,31,32,33,36,37,51]
H_PROCHOT#[54]
PCH_PECI[32]
JTAG_TDO [33]
JTAG_TDI [33]
JTAG_TMS [33]
JTAG_JTAGX [33]
JTAG_TRST# [37]
H_PREQ_N [37]
H_PRDY_N [37]
Title
Size Document Number Rev
Date: Sheet
of
6-71-N9500-D01A
D01A
[03] PROCESSOR 2/6
B
368Friday, October 06, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-N9500-D01A
D01A
[03] PROCESSOR 2/6
B
368Friday, October 06, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-N9500-D01A
D01A
[03] PROCESSOR 2/6
B
368Friday, October 06, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
R9 *1K_04
R7 *10K_04
R13 *1K_04
R8 *1K_04
R10 1K_04
R23 *0_04
R15 220_04
R25
1K_1%_04
R16 499_1%_04
R19 100_04
R3 56.2_1%_04
R11 *1K_04
R976 *0_04
R28
100K_04
R18 2.74K_1%_04
R977 *0_04
R12 *1K_04
U1E
SKL_S_CPU_LGA
6-86-25B51-001
lga1151
VCCST_PWRGD
U2
PM_SYNC
E8
PM_DOWN
D8
PECI
G7
VIDSOUT
E40
DDR_VTT_CNTL
AC36
CFG_18
G18
CFG_19
F18
PROC_TCK
F11
CFG_0
H15
PROC_TDO
H13
THERMTRIP#
D11
CFG_1
F15
PROC_TRST#
F12
PROC_SELECT#
AB36
CFG_2
F16
SKTOCC#
AC38
CFG_RCOMP
M11
CFG_3
H16
PROC_PREQ#
B9
CFG_4
F19
CFG_5
H18
CFG_10
F17
RESET#
E7
BCLKN
W4
CLK24N
J9
CFG_11
H17
CFG_6
G21
PROCPWRGD
F8
VIDSCK
E38
BPM#_0
D16
PCI_BCLKN
W2
CFG_7
H20
CFG_12
G20
BPM#_1
D17
BCLKP
W5
CLK24P
K9
CFG_8
G16
BPM#_2
G14
CFG_13
F20
PCI_BCLKP
W1
BPM#_3
H14
CFG_14
F21
CFG_9
E16
PROCHOT#
C39
CFG_15
H19
PROC_TDI
G12
CFG_16
E14
CATERR#
D13
PROC_PRDY#
B10
CFG_17
F14
PROC_TMS
F13
VIDALERT#
E39
Q1
2SK3018S3
G
DS
R978 *0_04
R5 1K_1%_04
R20 20_1%_04
R674 *0_04
R17 6.04K_1%_04
R14 *1K_04
C34
47P_50V_NPO_04
R979 *0_04
R21 51_04
R6 10K_04
R4 100_1%_04
R24 49.9_1%_04
R2303 620_04
H_PROCHOT#_R
CFG_RCOMP
CFG6
CFG7
CFG0
CFG2
CFG4
CFG5
CFG9
CPU_VIDALERT#
H_VIDALERT#_VR
H_VIDSOUT_VR
VCCST_PWRGD_CPU
H_PWRGD
H_PM_DOWN_R
H_SKTOCC#
H_TCK
H_TDO
H_PROCHOT#
DDR_VTT_PG_CTRL
DDR_VTT_PG_CTRL
H_VIDSOUT_VR
H_PRDY_N
H_PREQ_N
H_TRST_N
H_TCK
H_TMS
H_TDI
H_TDO
H_THERMTRIP#
H_THERMTRIP#
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