R11310K_1%_04
C430
0.047u_10V_X7R_04
R433 140_1%_04
3.3VS
R428
4.99K_1%_04
R38162_04
R424 25.5_1%_04
R436
1K_04
R60 *10mil_short
R380 56_1%_04
R114 *10mil_short
R432 200_1%_04
R129 *10mil_short
Q35
MTN7002ZHS3
G
DS
R435 *0_04
R128 *10mil_short
BUF_CPU_RST#
1.5V
1.05VS_VTT 2,5,23,24,25,41,42,44
1.05VS_VTT
3.3V 2,6,13,14,15,18,19,20,22,23,24,25,29,31,34,38,39,40,41
DRAMRST_CNTRL 6,19
DDR3_DRAMRST# 9,10,11,12
1.5V 6,9,10,11,12,25,38,40
CLK_EXP_N 19
CLK_EXP_P 19
1.5VS_CPU 6,38
H_PROCHOT#42
CPUDRAMRST#
H_THR MTR IP#23
H_PECI23,33
H_PM_SYNC20
H_CPUPWRGD23
H_CPUPWRGD_R
XD P_ D BR _ R
SKTOCC#
CAD Note: Capacitor need to be placed
close to buffer output pin
PMSYS_PWRGD_BUF
S
D
G
Q9B
MTDN7002ZHS6R
5
3
4
R396 51_04
R400 51_04
R389 51_04
R397 *51_04
R394 51_04
R3791K_04
R395 51_04
3.3VS
1.05VS_VTT
XDP_DBR_R
PU/PD for JTAG signals
XD P_ TMS
XD P_ TDO _ R
XD P_ TCL K
XD P_ TRS T#
XDP_PREQ#
XD P_ TDI _ R
S
D
G
Q9A
MTDN7002ZHS6R
2
6
1
C100 0.1u_16V_Y5V_04
R409 130_1%_04
PMSYS_PWRGD_BUF VDDPWRGOOD_R
R95
10K_04
SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0
PLT_R ST#13,14,22,54
XDP_TRST#
XD P_ TC LK
H_PROCHOT#_D
H_CATERR#
XD P_ TMS
CPUDRAMRST#
XDP_PREQ#
XD P_ TD I _R
XD P_ TD O_ R
R441 1K_04
S3 circuit:- DRAM_RST# to memory
should be high during S3
XDP_PRDY #
H_CPUPWRGD_R
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
U26B
Iv y Bridge_rPGA_2DPC_Rev 0p61
SM_RCOMP[1]
A5
SM_RCOMP[2]
A4
SM_DRAMRST#
R8
SM_RCOMP[0]
AK1
BCLK#
A27
BCLK
A28
DPLL_REF_CLK#
A15
DPLL_REF_CLK
A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
THE RMTR IP#
AN32
SM_DRAMPWROK
V8
RESET#
AR33
PRDY #
AP29
PREQ#
AP27
TCK
AR26
TMS
AR27
TRST#
AP30
TDI
AR28
TDO
AP26
DBR#
AL35
BPM#[0]
AT28
BPM#[1]
AR29
BPM#[2]
AR30
BPM#[3]
AT30
BPM#[4]
AP32
BPM#[5]
AR31
BPM#[6]
AT31
BPM#[7]
AR32
PM_SYNC
AM34
SKTOCC#
AN34
PROC_SELECT#
C26
UNCOREPWRGOOD
AP33
CLK_DP_P 19
C392
68P_50V_NPO_04
DDR3 Compensation Signals
TRACE WIDTH 10MIL, LENGTH <500MILS
BUF_CPU_RST#
CLK_DP_N 19
Processor Pullups/Pull downs
H_PROCHOT#
SM_RCOMP_1
SM_RCOMP_0
SM_RCOMP_2
H_PROCHOT#_EC33
R385
100K_04
R59
*750_1%_04
R386 *1.5K_1%_04
Q33
*MTN7002ZHS3
G
DS
R426
*39_04
R427
200_1%_04
R423
*200_04
R422
*100K_04
C429
*0.1u_16V_Y5V_04
R421 0_04
U28
*MC74VHC1G08DFT1G
1
2
5
4
3
3.3V
1.5VS_CPU
3.3V
SUSB38,39,40,41
1.8VS_PWRGD20,41
PM_DRAM_PWRGD20
S3 circuit:- DRAM PWR GOOD logic
1.05VS_VTT
If PROCHOT# is not used,
then it must be terminated
with a 56-£[ +-5% pull-up
resistor to 1.05VS_VTT .
Ivy Bridge Processor 2/7 ( CLK,MISC,JTAG )
R390
100K_04
BSS138 ( VGS 1.5V )
H_PROCHOT#
PROC_SELET
R58 43_1%_04
P150HM_D04A
Buffered reset to CPU
C379
47P_50V_NPO_04
3.3VS 9,10,11,12,13,14,15,16,17,18,19,20,22,23,24,25,27,28,29,30,31,32,33,34,35,38,42,44,54
Q26
MTN7002ZHS3
G
DS
H_SNB_IVB#23
R51
75_04
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