C278
*0.1u_16V_Y5V _04
H_PRO CH OT#
C31 5
0.047u_10V_X7R_04
R51 8 *1.5 K_ 1% _ 0 4
R517
*750_1%_04
H_CPU PW R GD _R
S3 circ uit: - DRAM PWR GOOD log ic
R174 130_1%_04
CAD Note: Capacitor need to be placed
close to buffer output pin
R512
75_04
R529 200_1%_04
R531 140_1%_04
R528 25.5_1%_04
R498 *10mil_short
R11 0 62_ 0 4
R515 43.2_1%_04
R499 10K_04
1.05VS_VTT
TRACE WIDTH 10MIL, LENGTH <500MILS
H_CPUPWRGD_R
Proces sor Pul lups /Pull do wns
H_PROCHOT#
R109 56_1%_04
1.05VS_VTT
3.3VS
1.05V S_V TT2,5,23,24,25,35,39
3.3V2,8,11,12,16,18,19,20,22,23,24,25,27,28,29,30,33,35, 37,38,39
CLK_EXP_N 19
CLK_EXP_P 19
1.5VS_C PU6,35,38
CLK_DP_P 19
CL K_ DP_ N 19
H_PROCHOT#39
H_THRMTRIP#23
H_ PECI23,34
H_PM_SYNC20
H_CP UPW R GD23
BUF_CPU_RST#
XDP _D BR_R
S
D
G
Q37A
MTD N7002ZH S6R
2
61
S
D
G
Q37B
MTDN7002ZHS6R
5
34
H _SNB_IVB#23
SM _RCO MP _2
SM _RCO MP _1
SM _RCO MP _0
XDP _TR ST#
XDP _TC LK
VDDPWRGOOD_R
H_PRO CH OT#_D
XDP _TM S
H_PR OC HO T#
CPUDRAMRST#
XDP _PR EQ#
XDP _TD I_R
XDP _TD O_R
R524
100K_04
If PROCHOT# is not used,
then it must be terminated
with a 56-O +-5% pull-up
resistor to 1.05VS_VTT .
DDR3 Compensation Signals
BUF_ C PU_ RST#
SM_RCOMP_1
SM_RCOMP_0
SM_RCOMP_2
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
U49B
PZ98827-364B-01F
SM _RC OM P[1]
A5
SM _RC OM P[2]
A4
SM_DR AMR ST#
R8
SM _RC OM P[0]
AK1
BC LK#
A27
BC LK
A28
DPLL_REF_SSC LK#
A15
DPLL_R EF_SSC LK
A16
CA TER R#
AL33
PEC I
AN33
PR OC HOT#
AL32
THER MTR IP#
AN32
SM _D RAM PW R OK
V8
RE SET#
AR33
PR DY #
AP29
PREQ #
AP27
TCK
AR26
TMS
AR27
TR S T #
AP30
TDI
AR28
TDO
AP26
DBR #
AL35
BPM # [0]
AT28
BPM # [1]
AR29
BPM # [2]
AR30
BPM # [3]
AT30
BPM # [4]
AP32
BPM # [5]
AR31
BPM # [6]
AT31
BPM # [7]
AR32
PM _SY NC
AM3 4
SKTOC C#
AN34
PR OC _SE LEC T#
C26
UN CO REP W RG OO D
AP33
C621
68p_50V_NPO _04
PLT_R ST#12,22,28
XDP _BP M0_R
XDP _BP M1_R
XDP _BP M2_R
R658
10K _04
1.5V6,8,9,10,25,29,35,37,38
XDP _BP M4_R
XDP _BP M3_R
XDP _BP M5_R
XDP _BP M6_R
XDP _BP M7_R
XDP _PR DY #
PM SYS _PW RG D_BUF
C62 2
47p_50V_N PO_04
R186 0_04
H_PR OCH OT# _ EC34
R203
100K_04
Sandy Bridge Processor 2/7 ( CLK,MISC,JTAG )
3.3VS9,10,11,12, 18,19,20,21,22, 23,24,25,27,28,29,30,31,32,33,34,35,39
Q1 6
MTN7002ZHS3
G
DS
Buffered reset to CPU
Q1 7
MTN7002ZHS3
G
DS
R225
4.99K_1%_04
CPU DR AMR ST#
R23 1 * 0_0 4
R230
1K_04
1.5V
S3 circ uit: - DRAM_RST# to memo ry
should be high during S3
DRAMRST_CNTRL 8,19
R235 1K_04
DD R3 _ DR AMR ST# 9 ,1 0
R51 351_04
R50 651_04
R51 051_04
R51 151_04
R50 551_04
R50 8*51_04
3.3V S
1.05VS_VTT
R494 1K_04
XD P _ T D O _ R
XD P_D BR _R
H_CATERR#
PU/PD f or JTA G sign als
XD P _ T R S T #
XD P _ T M S
H _SN B_IVB#
XD P_PREQ #
XD P _ T D I _ R
XD P _ T C L K
U14
*MC74VHC1G08DFT1G
1
2
5
4
3
1.8VS_PWRG D20,37
PM _D RA M_PW R GD20
3.3V
R187
*200_04
P MSY S_ PW RG D_BU F
R188
*100K_04
1.5VS_CP U
R175
200_1%_04
R168
*39_04
Q13
*MTN7002ZH S3
G
DS
SU SB35,37, 38
3.3V
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