CFG2
VREF_CH_A_DIMM
R51 4 10K_ 1%_ 0 4
3. 3 V
H_SN B_I VB#_PW R CTRL
H_C PU_ RSVD 2
H_C PU_ RSVD 1
H_C PU_ RSVD 4
H_C PU_ RSVD 3
MVREF_DQ_DIM1
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
CFG7
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
R642 *0_04
MVREF _D Q_DIM0
R643 *0_04
C367
0 . 1 u_ 1 0V _X 5 R _ 0 4
CFG6
CFG5
CFG 4
CFG 2
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG[6:5]
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
CFG2
Sandy Bridge Processor 7/7 ( RESERVED )
PCIE Port Bifurcation Straps
CFG4
CFG 7
RESERVED
U49E
PZ 98827-364B-01F
CFG[0]
AK28
CFG[1]
AK29
CFG[2]
AL26
CFG[3]
AL27
CFG[4]
AK26
CFG[5]
AL29
CFG[6]
AL30
CFG[7]
AM31
CFG[8]
AM32
CFG[9]
AM30
CFG[10]
AM28
CFG[11]
AM26
CFG[12]
AN28
CFG[13]
AN31
CFG[14]
AN26
CFG[15]
AM27
CFG[16]
AK31
CFG[17]
AN29
RSVD34
AM33
RSVD35
AJ27
RSVD38
J16
RSVD42
AT34
RSVD39
H16
RSVD40
G1 6
RSVD41
AR35
RSVD43
AT33
RSVD45
AR34
RSVD56
AT2
RSVD57
AT1
RSVD58
AR1
RSVD46
B34
RSVD47
A33
RSVD48
A34
RSVD49
B35
RSVD50
C35
RSVD51
AJ32
RSVD52
AK32
RSVD30
AE7
RSVD31
AK2
RSVD28
L7
RSVD29
AG7
RSVD27
J1 5
RSVD16
C30
RSVD15
D23
RSVD17
A31
RSVD18
B30
RSVD20
D30
RSVD19
B29
RSVD22
A30
RSVD21
B31
RSVD23
C29
RSVD24
J2 0
RSVD37
T8
RSVD6
B4
RSVD7
D1
RSVD8
F25
RSVD9
F24
RSVD11
D24
RSVD12
G2 5
RSVD13
G2 4
RSVD14
E23
RSVD32
W8
RSVD33
AT26
RSVD25
B18
RSVD44
AP35
RSVD10
F23
RSVD5
AJ26
VAXG_VAL_SENS E
AJ31
VSSAXG _VA L_SEN SE
AH31
VC C_VAL_S ENSE
AJ33
VSS_VAL_SENSE
AH33
KEY
B1
VCC _DIE_SENS E
AH27
VC CIO _SEL
A19
RSVD54
AN35
RSVD55
AM35
R516 *10mil_short H _SNB_IVB#_PW RC TR L _R
CFG7
CFG Straps for Processor
? DIM M? ? ? & TRAC E? ?
3.3V2,3,11,12,16,18,19,20,22,23,24,25,27,28,29,30, 33,35,37,38,39
CFG5
Display Port Presence Strap
1:(Default) Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG4
VR EF_C H_A_DIM M
R159
1K_1%_04
R500 *1K_04
Q9
*AO 3 40 2 L
G
DS
R491 * 1K_04
R153
*1 K_0 4
Q1 0
*AO 3 40 2 L
G
DS
R160
1K_1%_04
R149
*1 K_0 4
R15 5
1K _ 1 % _0 4
R492 *1K_04
R49 3 * 1K_ 0 4
R50 3 * 1K_ 0 4
R15 0
1K _ 1 % _0 4
1. 5 V
1.5V
DR AMR ST_C NTRL 3 ,1 9
D RAM RST_CN TR L 3,1 9
1.5V3,6,9,10, 25,29,35,37,38
CFG0
C357
0 . 1 u _1 0 V _ X 5R _0 4
MVRE F_DQ_DIMMA 9
CFG6
MVRE F_D Q_DIM MB 10
VREF_CH_B_DIMM
VR EF_C H_B_DIM M
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